A library and command-line tool for querying a Verilog netlist.
☆29Jun 13, 2022Updated 3 years ago
Alternatives and similar repositories for netlist-paths
Users that are interested in netlist-paths are comparing it to the libraries listed below
Sorting:
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 5 years ago
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 9 years ago
- ☆37Sep 19, 2024Updated last year
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆33Dec 25, 2025Updated 2 months ago
- ☆18Jul 9, 2025Updated 7 months ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- ☆22Jun 23, 2024Updated last year
- A header only C++11 library for functional coverage☆36Oct 5, 2022Updated 3 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆19Jul 22, 2020Updated 5 years ago
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- Python interface for cross-calling with HDL☆47Updated this week
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- FOSSi Foundation Website☆18Oct 5, 2024Updated last year
- This is a SpyDrNet Plugin for a physical design related transformations☆16Jun 13, 2025Updated 8 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Feb 25, 2023Updated 3 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Jul 23, 2025Updated 7 months ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆21Jul 24, 2025Updated 7 months ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- Alliance VLSI CAD Tools (LIP6)☆19Dec 11, 2025Updated 2 months ago
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago
- Resources from my class on computer architecture design☆10Apr 25, 2018Updated 7 years ago
- PLL Simulator in SystemC-AMS☆11Jun 2, 2023Updated 2 years ago
- cpp parser for reading a VCD (value change dump) file☆10Jul 15, 2013Updated 12 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆155Dec 9, 2025Updated 2 months ago
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Jan 14, 2022Updated 4 years ago
- A modern schematic entry and simulation program☆84Feb 23, 2026Updated last week
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆51Jan 13, 2021Updated 5 years ago
- IPXACT Register Map Generator☆11May 9, 2021Updated 4 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 2 years ago
- Experiments for iCEstick evaluation board with iCE40HX-1k FPGA - using open source toolchain☆13Nov 24, 2015Updated 10 years ago
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 7 months ago