jameshanlon / netlist-paths
A library and command-line tool for querying a Verilog netlist.
☆26Updated 2 years ago
Alternatives and similar repositories for netlist-paths:
Users that are interested in netlist-paths are comparing it to the libraries listed below
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 9 months ago
- ☆31Updated last year
- ☆44Updated 5 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆51Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- Cross EDA Abstraction and Automation☆37Updated last week
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆34Updated 4 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆34Updated 5 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 9 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- An automatic clock gating utility☆47Updated 2 weeks ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 4 years ago
- Extended and external tests for Verilator testing☆16Updated last week
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆51Updated 3 years ago
- ☆36Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 2 months ago
- Mirror of tachyon-da cvc Verilog simulator☆43Updated last year
- Open source RTL simulation acceleration on commodity hardware☆25Updated 2 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated 8 months ago
- ☆33Updated 2 years ago
- ☆20Updated 3 years ago
- Python/Simulator integration using procedure calls☆10Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- CMake based hardware build system☆16Updated this week