jameshanlon / netlist-pathsLinks
A library and command-line tool for querying a Verilog netlist.
☆29Updated 3 years ago
Alternatives and similar repositories for netlist-paths
Users that are interested in netlist-paths are comparing it to the libraries listed below
Sorting:
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Updated 2 years ago
- Cross EDA Abstraction and Automation☆40Updated last month
- ☆31Updated 2 years ago
- A header only C++11 library for functional coverage☆36Updated 3 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last month
- CMake based hardware build system☆35Updated 3 weeks ago
- ☆44Updated 5 years ago
- ☆13Updated 3 years ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- Constrained RAndom Verification Enviroment (CRAVE)☆18Updated 2 years ago
- Xilinx Unisim Library in Verilog☆86Updated 5 years ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- SystemVerilog Linter based on pyslang☆31Updated 8 months ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆42Updated 5 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆28Updated 2 months ago
- An open source PDK using TIGFET 10nm devices.☆54Updated 3 years ago
- Collection of test cases for Yosys☆17Updated 4 years ago
- ☆33Updated last year
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆88Updated last year
- Open Source PHY v2☆32Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- Open source RTL simulation acceleration on commodity hardware☆33Updated 2 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆68Updated 10 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆44Updated 2 years ago
- A SystemVerilog source file pickler.☆60Updated last year