A library and command-line tool for querying a Verilog netlist.
☆29Jun 13, 2022Updated 3 years ago
Alternatives and similar repositories for netlist-paths
Users that are interested in netlist-paths are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SVA examples and demonstration☆18Sep 8, 2020Updated 5 years ago
- Python/Simulator integration using procedure calls☆10Mar 12, 2020Updated 6 years ago
- ☆37Sep 19, 2024Updated last year
- Virtual development board for HDL design☆42Mar 31, 2023Updated 2 years ago
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆34Dec 25, 2025Updated 2 months ago
- A basic documentation generator for Verilog, similar to Doxygen.☆13Aug 5, 2016Updated 9 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Feb 25, 2023Updated 3 years ago
- ☆18Jul 9, 2025Updated 8 months ago
- A header only C++11 library for functional coverage☆36Oct 5, 2022Updated 3 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- ☆10Apr 8, 2021Updated 4 years ago
- Web-based HDL diagramming tool☆83May 1, 2023Updated 2 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- Experiments for iCEstick evaluation board with iCE40HX-1k FPGA - using open source toolchain☆13Nov 24, 2015Updated 10 years ago
- Oombak 🌊 is an interactive SystemVerilog simulator UI that runs on your terminal!☆48Oct 11, 2025Updated 5 months ago
- SystemVerilog wrapper over the Verilog Programming Interface (VPI)☆13Jun 3, 2025Updated 9 months ago
- Python interface for cross-calling with HDL☆49Mar 14, 2026Updated last week
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated 8 months ago
- A complete open-source design-for-testing (DFT) Solution☆183Aug 30, 2025Updated 6 months ago
- Alliance VLSI CAD Tools (LIP6)☆20Dec 11, 2025Updated 3 months ago
- A simple function to add wavedrom diagrams into an ipython notebook.☆24Jan 14, 2022Updated 4 years ago
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆156Dec 9, 2025Updated 3 months ago
- PLL Simulator in SystemC-AMS☆11Jun 2, 2023Updated 2 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆12Jan 17, 2024Updated 2 years ago
- Python library for operations with VCD and other digital wave files☆55Nov 12, 2025Updated 4 months ago
- HTML & Js based VCD viewer☆74Feb 16, 2026Updated last month
- Reflection API for SystemVerilog☆15Jun 5, 2025Updated 9 months ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Oct 15, 2024Updated last year
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Sep 20, 2023Updated 2 years ago
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- Python implementations of fixed size hardware types (Bit, BitVector, UInt, SInt, ...) based on the SMT-LIB2 semantics☆18Sep 13, 2023Updated 2 years ago
- Public repository for PySysC, (From SC Common Practices Subgroup)☆54Dec 26, 2023Updated 2 years ago
- a project to check the FOSS synthesizers against vendors EDA tools☆12Sep 26, 2020Updated 5 years ago
- FOSSi Foundation Website☆19Oct 5, 2024Updated last year
- OpenROAD Agent. This repository contain the model to train and testing the model using EDA Corpus dataset.☆22Jul 24, 2025Updated 8 months ago
- A simple Python utility for extracting documentation snippets from tutorials.☆14Aug 7, 2023Updated 2 years ago
- A VHDL Core Library.☆18Mar 29, 2017Updated 8 years ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆82Feb 9, 2022Updated 4 years ago