sepandhaghighi / verilogparser
Simple Verilog Parser In Python
☆15Updated 7 years ago
Alternatives and similar repositories for verilogparser:
Users that are interested in verilogparser are comparing it to the libraries listed below
- Open-Source Framework for Co-Emulation☆11Updated 4 years ago
- Constrained RAndom Verification Enviroment (CRAVE)☆17Updated last year
- Platform Level Interrupt Controller☆38Updated 11 months ago
- SystemVerilog FSM generator☆30Updated 11 months ago
- SystemC simulator of a highly customizable Nostrum network-on-chip (NoC).☆14Updated 10 years ago
- Hardware Formal Verification☆15Updated 4 years ago
- Modular Multi-ported SRAM-based Memory☆29Updated 5 months ago
- UVM Python Verification Agents Library☆14Updated 4 years ago
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 3 years ago
- Ratatoskr NoC Simulator☆24Updated 3 years ago
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 5 years ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 9 months ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆29Updated 8 months ago
- Network on Chip for MPSoC☆26Updated last week
- OpenDesign Flow Database☆16Updated 6 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- DUTH RISC-V Superscalar Microprocessor☆30Updated 5 months ago
- ☆25Updated this week
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆26Updated 6 months ago
- Generate testbench for your verilog module.☆37Updated 7 years ago
- Tools for working with circuits as graphs in python☆114Updated last year
- Some simple examples for the Magic VLSI physical chip layout tool.☆29Updated 4 years ago
- LLVM based HLS library for HWToolkit (hardware devel. toolkit)☆25Updated 4 months ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆32Updated 2 months ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces☆17Updated 11 months ago
- A repository for SystemC Learning examples☆67Updated 2 years ago