Alternatives and similar repositories for verilog-dot:

Users that are interested in verilog-dot are comparing it to the libraries listed below

• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆32Updated last month
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• freecores / robust_axi_fabric
  Generic AXI interconnect fabric
  ☆13Updated 10 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆41Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• VP-Vibes / VPV-Peripherals
  Library of example SystemC/TLM peripherals for various SoCs based on the SCS library
  ☆12Updated 2 weeks ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆43Updated last month
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆31Updated 3 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated last year
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆64Updated last month
• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆24Updated 2 years ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 2 months ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• pulp-platform / axi_llc
  ☆25Updated last week
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆50Updated last year
• Risto97 / systemc_uvm_verilator
  ☆11Updated 2 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 4 years ago
• sequencer / arithmetic
  ☆32Updated 2 weeks ago
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆41Updated 3 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆26Updated 6 months ago
• jimmysitu / vtags
  Verdi like, verilog code signal trace and show hierarchy script
  ☆19Updated 5 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆30Updated 5 months ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆27Updated 11 months ago
• MikeCovrado / GettingVerilatorStartedWithUVM
  Simple UVM environment for experimenting with Verilator.
  ☆19Updated 3 months ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆37Updated 2 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆33Updated 4 months ago
• maltanar / systemc-chisel-tools
  A collection of tools for working with Chisel-generated hardware in SystemC
  ☆16Updated 5 years ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 8 months ago