ben-marshall / verilog-dot

Related projects ⓘ

Alternatives and complementary repositories for verilog-dot

• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆16Updated 11 months ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 4 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆39Updated 4 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆31Updated 2 weeks ago
• freecores / robust_axi_fabric
  Generic AXI interconnect fabric
  ☆12Updated 10 years ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• povik / yosys-slang
  slang-based frontend for Yosys
  ☆41Updated this week
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 3 months ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 2 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆15Updated 2 weeks ago
• cclienti / svmodule
  SystemVerilog & Verilog Module I/O parser and printer
  ☆25Updated 3 years ago
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆25Updated 6 months ago
• agra-uni-bremen / crave
  Constrained random stimuli generation for C++ and SystemC
  ☆49Updated 11 months ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆44Updated 2 years ago
• alainmarcel / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Li…
  ☆25Updated last month
• aolofsson / POSH
  ☆39Updated 4 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆78Updated last month
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆30Updated 3 years ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated last year
• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆24Updated last year
• verilog-to-routing / libblifparse
  Parsing library for BLIF netlists
  ☆18Updated last week
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• IBM / esp-chisel-accelerators
  Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
  ☆23Updated 4 years ago
• funningboy / pyvpi_example
  use pivpi to drive testbench event
  ☆20Updated 8 years ago
• jimmysitu / vtags
  Verdi like, verilog code signal trace and show hierarchy script
  ☆19Updated 5 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆38Updated 4 months ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆92Updated 7 months ago