Alternatives and similar repositories for PyVerilog

Users that are interested in PyVerilog are comparing it to the libraries listed below

• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆32Updated 10 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆71Updated 7 months ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• SystemRDL / PeakRDL-uvm
  Generate UVM register model from compiled SystemRDL input
  ☆60Updated 2 months ago
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆26Updated 4 years ago
• greenblat / vlsistuff
  ideas and eda software for vlsi design
  ☆51Updated 2 weeks ago
• fukatani / Pyverilog_toolbox
  ☆43Updated 7 years ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆39Updated 9 years ago
• fvutils / pyvsc
  Python packages providing a library for Verification Stimulus and Coverage
  ☆137Updated 2 weeks ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 2 months ago
• sgherbst / svreal
  Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
  ☆51Updated 5 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 6 months ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆63Updated 4 years ago
• accellera / uvm
  ☆60Updated 9 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆75Updated this week
• systemc / uvmc
  Connecting SystemC with SystemVerilog
  ☆41Updated 13 years ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆75Updated 5 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆76Updated 5 years ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆178Updated 5 months ago
• chiggs / UVM
  Mirror of the Universal Verification Methodology from sourceforge
  ☆36Updated 11 years ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆83Updated 4 years ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆64Updated this week
• sgherbst / pysvinst
  Python library for parsing module definitions and instantiations from SystemVerilog files
  ☆26Updated 4 years ago
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆52Updated 10 months ago
• funningboy / vim
  UVM/systemverilog/verilog/python VIM IDE
  ☆16Updated 12 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆65Updated 5 years ago
• intel / aib-phy-hardware
  ☆68Updated 3 years ago
• SeanOBoyle / DoxygenFilterSystemVerilog
  ☆40Updated 10 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆48Updated last year