Alternatives and similar repositories for verilog-doc

Users that are interested in verilog-doc are comparing it to the libraries listed below

• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆18Updated last year
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆28Updated 3 years ago
• SystemRDL / PeakRDL-ipxact
  Import and export IP-XACT XML register models
  ☆35Updated this week
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆26Updated 9 years ago
• SymbiFlow / sphinx-verilog-domain
  Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.
  ☆25Updated 4 years ago
• amiq-consulting / fc4sc
  A header only C++11 library for functional coverage
  ☆36Updated 3 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆41Updated 2 weeks ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆40Updated 2 weeks ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆29Updated last year
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated 2 months ago
• pybfms / pybfms
  Provides automation scripts for building BFMs
  ☆16Updated 6 months ago
• SpinalHDL / CocotbLib
  ☆18Updated 4 months ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆54Updated last year
• tudortimi / ipxact
  IP-XACT XML binding library
  ☆16Updated 9 years ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 10 months ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆14Updated 9 months ago
• amiq-consulting / uvm_reg_to_ipxact
  ☆16Updated 6 years ago
• jg-fossh / uvm-python-verification-lib
  UVM Python Verification Agents Library
  ☆15Updated 4 years ago
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated 2 weeks ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 6 years ago
• PyHDI / ipgen
  IP-core package generator for AXI4/Avalon
  ☆22Updated 6 years ago
• JoseIuri / UVM_Python
  This repository contains an example of the connection between an UVM Testbench and a Python reference model.
  ☆11Updated 6 years ago
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 6 months ago
• go2uvm / go2uvm
  Main repo for Go2UVM source code, examples and apps
  ☆21Updated 2 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 5 months ago
• Risto97 / systemc_uvm_verilator
  ☆13Updated 3 years ago
• YosysHQ-GmbH / SVA-AXI4-FVIP
  YosysHQ SVA AXI Properties
  ☆43Updated 2 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago