Synopsys Design compiler, VCS and Tetra-MAX
☆19May 29, 2018Updated 8 years ago
Alternatives and similar repositories for Tool-Make-Script
Users that are interested in Tool-Make-Script are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Syno…☆14Jun 9, 2021Updated 5 years ago
- Synopsys Verdi applet that presents a view of the source code running on a RISC-V processor with a simulation waveform.☆34Feb 6, 2020Updated 6 years ago
- Tests for the design flow with Synopsys tools for the implementation of a RISC-V processor.☆28Sep 8, 2024Updated 2 years ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- ☆10Aug 30, 2024Updated 2 years ago
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 5 years ago
- ☆10Apr 8, 2021Updated 5 years ago
- This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…☆32Apr 29, 2024Updated 2 years ago
- Various low power labs using sky130☆13Sep 3, 2021Updated 5 years ago
- This is a tutorial on standard digital design flow☆86May 24, 2021Updated 5 years ago
- Some useful documents of Synopsys☆119Nov 5, 2021Updated 4 years ago
- APB4 Multiplexor☆15May 10, 2024Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆27Oct 1, 2026Updated last week
- Verification of Ethernet Switch System Verilog☆12Oct 21, 2016Updated 9 years ago
- SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow☆58Feb 27, 2026Updated 7 months ago
- A simple tool to demonstrate the physical design steps of VLSI Design Flow.☆11Dec 13, 2020Updated 5 years ago
- 学习AXI接口，以及xilinx DDR3 IP使用☆40Mar 6, 2017Updated 9 years ago
- Revision Control Labs and Materials☆26Jan 23, 2018Updated 8 years ago
- RISC-V ISA based 32-bit processor written in HLS☆16Nov 7, 2019Updated 6 years ago
- A tiny FP8 multiplication unit written in Verilog. TinyTapeout 2 submission.☆14Nov 23, 2022Updated 3 years ago
- Eric's branch of Doxverilog (doxygen + doxverilog patch)☆15Jun 6, 2012Updated 14 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Generate UVM testbench framework template files with Python 3☆26Dec 23, 2019Updated 6 years ago
- Examples of unions, interfaces, and assertions in SystemVerilog☆14Aug 31, 2013Updated 13 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 7 years ago
- Verilog+VHDL Hierarchy Management tool ( IDE ) wraps around Vim, runs in Linux terminal window.☆13Jan 15, 2017Updated 9 years ago
- Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library☆38Jan 18, 2022Updated 4 years ago
- 平头哥无剑100开源SoC平台（双核E902，安全启动，BootROM，IOPMP，Mailbox，RSA-2048，SHA-2， WS2812，Flash）☆23Sep 2, 2023Updated 3 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Example files for the book FPGA SIMULATION☆23Apr 6, 2017Updated 9 years ago
- Example of a full DC synthesis script for a simple design☆14Feb 25, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- IEEE Executive project for the year 2021-2022☆15Nov 22, 2022Updated 3 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆28Oct 8, 2018Updated 8 years ago
- Black Duck Detect plugin for Jenkins☆12Aug 27, 2026Updated last month
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Implementation of the PCIe physical layer☆64Jul 11, 2025Updated last year
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- Architectural design of data router in verilog☆33Dec 29, 2019Updated 6 years ago