jomonkjoy / Tool-Make-ScriptLinks
Synopsys Design compiler, VCS and Tetra-MAX
☆19Updated 7 years ago
Alternatives and similar repositories for Tool-Make-Script
Users that are interested in Tool-Make-Script are comparing it to the libraries listed below
Sorting:
- General Purpose AXI Direct Memory Access☆57Updated last year
- Implementation of the PCIe physical layer☆48Updated last month
- SoC Based on ARM Cortex-M3☆32Updated 3 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- ☆26Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- ☆29Updated 5 years ago
- UVM resource from github, run simulation use YASAsim flow☆28Updated 5 years ago
- AXI Interconnect☆52Updated 4 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆16Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- DOULOS Easier UVM Code Generator☆34Updated 8 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆33Updated 3 months ago
- ☆20Updated 2 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 7 months ago
- System on Chip verified with UVM/OSVVM/FV☆31Updated 3 months ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- ☆36Updated 10 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆29Updated 2 months ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- UART design in SV and verification using UVM and SV☆47Updated 5 years ago
- ☆60Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆23Updated 6 months ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆28Updated 8 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago