Alternatives and similar repositories for Verilog:

Users that are interested in Verilog are comparing it to the libraries listed below

• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆35Updated 11 months ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆31Updated 9 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• Nic30 / hwtHls
  LLVM based HLS library for HWToolkit (hardware devel. toolkit)
  ☆25Updated 2 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆38Updated 2 months ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆41Updated 7 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆35Updated 3 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 8 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated this week
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 5 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆51Updated this week
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆21Updated 3 years ago
• VLSIDA / OpenCache
  An open-source custom cache generator.
  ☆30Updated 11 months ago
• sifive / duh
  👾 Design ∪ Hardware
  ☆74Updated 3 months ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆30Updated 3 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆67Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆54Updated 2 years ago
• efabless / caravel-lite
  ☆15Updated 3 months ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆24Updated 2 years ago
• ucb-bar / OpenSoCFabric
  OpenSoC Fabric - A Network-On-Chip Generator
  ☆17Updated 7 years ago
• rochus-keller / Coco
  Compiler Generator Coco/R modified for VerilogEbnf
  ☆9Updated 5 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated last week
• drom / logidrom
  Digital Circuit rendering engine
  ☆37Updated last year