Alternatives and similar repositories for Verilog

Users that are interested in Verilog are comparing it to the libraries listed below

• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆35Updated 2 weeks ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆35Updated this week
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 8 months ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆27Updated 2 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆98Updated 3 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆50Updated 10 years ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 5 years ago
• ArchC / ArchC
  A powerful and modern open-source architecture description language.
  ☆45Updated 8 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆48Updated 5 months ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated last month
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆38Updated 4 years ago
• bobbl / rudolv
  RISC-V processor
  ☆32Updated 3 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆59Updated 4 years ago
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆35Updated 5 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆17Updated 3 years ago
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆53Updated 6 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆103Updated 4 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆19Updated 2 years ago
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆87Updated 5 years ago
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆106Updated 3 months ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• HardwareIR / netlistDB
  netlistDB - Intermediate format for digital hardware representation with graph database API
  ☆32Updated 4 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆149Updated 2 weeks ago
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆38Updated 11 months ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• riscv / riscv-test-env
  ☆50Updated 2 months ago