ben-marshall / verilog-vcd-parser
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
☆90Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for verilog-vcd-parser
- A Standalone Structural Verilog Parser☆83Updated 2 years ago
- Introductory course into static timing analysis (STA).☆63Updated last week
- Python packages providing a library for Verification Stimulus and Coverage☆113Updated last month
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆75Updated last week
- Re-coded Xilinx primitives for Verilator use☆41Updated 8 months ago
- ☆38Updated last month
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆73Updated 7 months ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆121Updated 9 months ago
- ☆42Updated 8 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- Mirror of Synopsys's Liberty parser library☆18Updated 6 years ago
- IDEA project source files☆97Updated 2 months ago
- Python bindings for slang, a library for compiling SystemVerilog☆45Updated this week
- A Fast, Low-Overhead On-chip Network☆134Updated 2 weeks ago
- AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BR…☆97Updated 8 months ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆94Updated 3 weeks ago
- Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.☆75Updated 6 months ago
- Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits☆55Updated 5 months ago
- Collection of digital hardware modules & projects (benchmarks)☆31Updated last week
- SystemVerilog & Verilog Module I/O parser and printer☆25Updated 3 years ago
- Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.☆52Updated 3 months ago
- RISC-V Verification Interface☆74Updated 2 months ago
- A Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.☆128Updated 5 years ago
- ☆73Updated last year
- A complete open-source design-for-testing (DFT) Solution☆135Updated last week
- reference block design for the ASAP7nm library in Cadence Innovus☆32Updated 4 months ago
- ☆30Updated last year
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated this week
- Material for OpenROAD Tutorial at DAC 2020☆46Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆58Updated last week