Alternatives and similar repositories for euvm

Users that are interested in euvm are comparing it to the libraries listed below

• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆17Updated last year
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated last year
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆27Updated 4 years ago
• dpretet / svlogger
  SystemVerilog Logger
  ☆17Updated 2 years ago
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆17Updated last year
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆37Updated 5 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆29Updated 10 months ago
• fvutils / pyucis
  Python API to Unified Coverage Interoperability Standard (UCIS) Data
  ☆24Updated 2 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• TUM-LIS / lisnoc
  LIS Network-on-Chip Implementation
  ☆29Updated 8 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆28Updated 7 months ago
• pulp-platform / axi2apb
  ☆20Updated 5 years ago
• fvutils / py-hpi
  Python/Simulator integration using procedure calls
  ☆10Updated 5 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated 3 weeks ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated last year
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆25Updated 8 years ago
• scarv / scarv-cpu
  SCARV: a side-channel hardened RISC-V platform
  ☆26Updated 2 years ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆68Updated 9 months ago
• AsFigo / apb_uvc_verilator
  APB UVC ported to Verilator
  ☆11Updated last year
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆39Updated 5 years ago
• avidan-efody / wave_rerunner
  Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.
  ☆59Updated 3 years ago
• verilator / example-systemverilog
  ☆38Updated last year
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆52Updated 11 months ago
• avidan-efody / wave_searcher
  Implementation of post-process coverage, and batch waveform search
  ☆15Updated 3 years ago
• mciepluc / apbi2c_cocotb_example
  An example Python-based MDV testbench for apbi2c core
  ☆30Updated 9 months ago
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆22Updated 4 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆29Updated last week