lowRISC Style Guides
☆506Apr 21, 2026Updated last month
Alternatives and similar repositories for style-guides
Users that are interested in style-guides are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆607Jan 3, 2026Updated 4 months ago
- Common SystemVerilog components☆751Updated this week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,846Mar 13, 2026Updated 2 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆668May 11, 2026Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,584May 19, 2026Updated last week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Code generation tool for control and status registers☆455Apr 19, 2026Updated last month
- Random instruction generator for RISC-V processor verification☆1,303Apr 3, 2026Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,883May 7, 2026Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,235Apr 17, 2026Updated last month
- Generic Register Interface (contains various adapters)☆140May 15, 2026Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆375Updated this week
- SystemVerilog to Verilog conversion☆728Mar 28, 2026Updated last month
- A dependency management tool for hardware projects.☆370Updated this week
- SystemVerilog linter☆383Nov 6, 2025Updated 6 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆981Nov 15, 2024Updated last year
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆472Mar 30, 2026Updated last month
- Functional verification project for the CORE-V family of RISC-V cores.☆683Apr 16, 2026Updated last month
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆35Oct 12, 2025Updated 7 months ago
- cocotb: Python-based chip (RTL) verification☆2,379Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆603May 7, 2026Updated 2 weeks ago
- An abstraction library for interfacing EDA tools☆770Apr 24, 2026Updated last month
- Contains the code examples from The UVM Primer Book sorted by chapters.☆625Dec 24, 2021Updated 4 years ago
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆531May 10, 2026Updated 2 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- AMBA AXI VIP☆459Jun 28, 2024Updated last year
- OpenTitan: Open source silicon root of trust☆3,376May 19, 2026Updated last week
- Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM☆45Jul 11, 2025Updated 10 months ago
- SystemVerilog compiler and language services☆1,039May 16, 2026Updated last week
- RISC-V Debug Support for our PULP RISC-V Cores☆311Apr 1, 2026Updated last month
- RISC-V Verification Interface☆152Mar 27, 2026Updated last month
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,947Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,622Updated this week
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The UVM written in Python☆542May 18, 2026Updated last week
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆289Nov 25, 2019Updated 6 years ago
- Verilog AXI components for FPGA implementation☆2,052Feb 27, 2025Updated last year
- A Fast, Low-Overhead On-chip Network☆295May 12, 2026Updated 2 weeks ago
- VeeR EL2 Core☆338Updated this week
- This is the repository for the IEEE version of the book☆81Sep 29, 2020Updated 5 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆482May 8, 2026Updated 2 weeks ago