Alternatives and similar repositories for style-guides

Users that are interested in style-guides are comparing it to the libraries listed below

• pyuvm / pyuvm
  The UVM written in Python
  ☆491Updated 2 weeks ago
• pulp-platform / common_cells
  Common SystemVerilog components
  ☆692Updated 3 weeks ago
• bespoke-silicon-group / basejump_stl
  BaseJump STL: A Standard Template Library for SystemVerilog
  ☆632Updated 2 weeks ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆305Updated 3 months ago
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆618Updated 8 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆354Updated this week
• zachjs / sv2v
  SystemVerilog to Verilog conversion
  ☆693Updated last month
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆451Updated 7 months ago
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆403Updated last year
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆407Updated 3 months ago
• openhwgroup / cvfpu
  Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
  ☆557Updated 2 months ago
• rggen / rggen
  Code generation tool for control and status registers
  ☆439Updated this week
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆556Updated last week
• svunit / svunit
  ☆207Updated 10 months ago
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆434Updated 4 months ago
• raysalemi / uvmprimer
  Contains the code examples from The UVM Primer Book sorted by chapters.
  ☆591Updated 4 years ago
• ben-marshall / awesome-open-hardware-verification
  A List of Free and Open Source Hardware Verification Tools and Frameworks
  ☆581Updated last week
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆636Updated this week
• pulp-platform / pulp
  This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain a…
  ☆533Updated last year
• tpoikela / uvm-python
  UVM 1.2 port to Python
  ☆257Updated 11 months ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆438Updated last year
• TerosTechnology / vscode-terosHDL
  VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
  ☆682Updated 3 weeks ago
• UVVM / UVVM
  UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …
  ☆419Updated 2 weeks ago
• accellera-official / uvm-core
  ☆106Updated last year
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆352Updated this week
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆447Updated this week
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆340Updated 3 years ago
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆245Updated last year
• VerificationExcellence / SystemVerilogReference
  training labs and examples
  ☆443Updated 3 years ago
• olofk / edalize
  An abstraction library for interfacing EDA tools
  ☆737Updated 3 weeks ago