lowRISC Style Guides
☆522Jul 8, 2026Updated 2 weeks ago
Alternatives and similar repositories for style-guides
Users that are interested in style-guides are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆615Jan 3, 2026Updated 6 months ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,895Jul 19, 2026Updated last week
- Common SystemVerilog components☆769Updated this week
- BaseJump STL: A Standard Template Library for SystemVerilog☆676Jul 7, 2026Updated 2 weeks ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,631Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Code generation tool for control and status registers☆463Jul 16, 2026Updated last week
- Random instruction generator for RISC-V processor verification☆1,330Apr 3, 2026Updated 3 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,267May 29, 2026Updated last month
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,987Jul 14, 2026Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆382Updated this week
- Generic Register Interface (contains various adapters)☆141Updated this week
- A dependency management tool for hardware projects.☆379Updated this week
- SystemVerilog to Verilog conversion☆741Mar 28, 2026Updated 3 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆990Nov 15, 2024Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- SystemVerilog linter☆388Nov 6, 2025Updated 8 months ago
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆478Jun 10, 2026Updated last month
- Functional verification project for the CORE-V family of RISC-V cores.☆703Jul 17, 2026Updated last week
- cocotb: Python-based chip (RTL) verification☆2,455Updated this week
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆624Updated this week
- Contains the code examples from The UVM Primer Book sorted by chapters.☆642Dec 24, 2021Updated 4 years ago
- An abstraction library for interfacing EDA tools☆781Jul 2, 2026Updated 3 weeks ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆39Nov 6, 2025Updated 8 months ago
- AMBA AXI VIP☆467Jun 28, 2024Updated 2 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- OpenTitan: Open source silicon root of trust☆3,562Updated this week
- The UVM written in Python☆561Updated this week
- RISC-V Verification Interface☆157Jun 11, 2026Updated last month
- RISC-V Debug Support for our PULP RISC-V Cores☆316Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,035Updated this week
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆37Jun 24, 2026Updated last month
- SystemVerilog compiler and language services☆1,093Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,773Updated this week
- CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.☆290Nov 25, 2019Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Verilog AXI components for FPGA implementation☆2,097Feb 27, 2025Updated last year
- VeeR EL2 Core☆342Updated this week
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆488May 8, 2026Updated 2 months ago
- Verilog/SystemVerilog Syntax and Omni-completion☆420Oct 13, 2024Updated last year
- ☆222May 30, 2026Updated last month
- Package manager and build abstraction tool for FPGA/ASIC development☆1,440Jul 2, 2026Updated 3 weeks ago
- A Linux-capable RISC-V multicore for and by the world☆823Jul 13, 2026Updated last week