CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
☆287Nov 25, 2019Updated 6 years ago
Alternatives and similar repositories for logic
Users that are interested in logic are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Virtio implementation in SystemVerilog☆49Jan 23, 2018Updated 8 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆15Mar 2, 2022Updated 4 years ago
- Customized UVM Report Server☆42Feb 10, 2020Updated 6 years ago
- UVM 1.2 port to Python☆261Feb 9, 2025Updated last year
- SystemC/TLM-2.0 Co-simulation framework☆277May 21, 2025Updated 10 months ago
- Wordpress hosting with auto-scaling on Cloudways • AdFully Managed hosting built for WordPress-powered businesses that need reliable, auto-scalable hosting. Cloudways SafeUpdates now available.
- Lightweight unit testing framework for C/C++ projects. Suitable for embedded devices.☆20Feb 21, 2017Updated 9 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆132Apr 2, 2026Updated last week
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,807Mar 13, 2026Updated 3 weeks ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,407Feb 13, 2026Updated last month
- ☆13Aug 22, 2022Updated 3 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆207Oct 21, 2024Updated last year
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆80Oct 22, 2024Updated last year
- An abstraction library for interfacing EDA tools☆757Apr 1, 2026Updated last week
- SystemVerilog compiler and language services☆1,002Updated this week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- SystemC Reference Implementation☆653Mar 24, 2026Updated 2 weeks ago
- VUnit is a unit testing framework for VHDL/SystemVerilog☆821Apr 4, 2026Updated last week
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆223Dec 23, 2025Updated 3 months ago
- AMBA AXI VIP☆453Jun 28, 2024Updated last year
- A simple C++ CMake project to jump-start development of SystemC models and systems☆30Nov 24, 2024Updated last year
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆457Apr 5, 2026Updated last week
- Code generation tool for control and status registers☆452Apr 2, 2026Updated last week
- JTAG DPI module for OpenRISC simulation with Verilator☆18Oct 27, 2012Updated 13 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆70Feb 13, 2025Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Network on Chip Implementation written in SytemVerilog☆200Aug 27, 2022Updated 3 years ago
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆599Jan 3, 2026Updated 3 months ago
- SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)☆74Jan 14, 2021Updated 5 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆616Dec 24, 2021Updated 4 years ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆603Jul 30, 2025Updated 8 months ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆72Dec 17, 2025Updated 3 months ago
- cocotb: Python-based chip (RTL) verification☆2,312Apr 2, 2026Updated last week
- Test suite designed to check compliance with the SystemVerilog standard.☆371Updated this week
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆302Updated this week
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Constrained random stimuli generation for C++ and SystemC☆53Nov 29, 2023Updated 2 years ago
- RISC-V SystemC-TLM simulator☆348Feb 20, 2026Updated last month
- Common SystemVerilog components☆733Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆471Mar 30, 2026Updated last week
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 7 years ago
- A modeling library with virtual components for SystemC and TLM simulators☆186Apr 4, 2026Updated last week
- Repurposing existing HDL tools to help writing better code☆221Jun 6, 2024Updated last year