CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
☆291Nov 25, 2019Updated 6 years ago
Alternatives and similar repositories for logic
Users that are interested in logic are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Virtio implementation in SystemVerilog☆50Jan 23, 2018Updated 8 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Customized UVM Report Server☆41Feb 10, 2020Updated 6 years ago
- UVM 1.2 port to Python☆262Feb 9, 2025Updated last year
- SystemC/TLM-2.0 Co-simulation framework☆307Jun 26, 2026Updated 2 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆139Sep 5, 2026Updated 2 weeks ago
- Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server☆1,938Updated this week
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆208Jun 3, 2026Updated 3 months ago
- Package manager and build abstraction tool for FPGA/ASIC development☆1,461Sep 12, 2026Updated last week
- ☆13Aug 22, 2022Updated 4 years ago
- AMBA AXI VIP☆477Jun 28, 2024Updated 2 years ago
- An abstraction library for interfacing EDA tools☆795Updated this week
- SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!☆82Oct 22, 2024Updated last year
- SystemC Reference Implementation☆691Sep 8, 2026Updated last week
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- SystemVerilog compiler and language services☆1,144Updated this week
- VUnit is a unit testing framework for VHDL/SystemVerilog☆844Sep 11, 2026Updated last week
- A simple C++ CMake project to jump-start development of SystemC models and systems☆31Nov 24, 2024Updated last year
- VHDL/Verilog/SystemC code generator, simulator API written in python/c++☆226Aug 25, 2026Updated 3 weeks ago
- SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…☆475Updated this week
- JTAG DPI module for OpenRISC simulation with Verilator☆18Oct 27, 2012Updated 13 years ago
- Code generation tool for control and status registers☆471Sep 11, 2026Updated last week
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆71Feb 13, 2025Updated last year
- Network on Chip Implementation written in SytemVerilog☆212Aug 27, 2022Updated 4 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- A List of Free and Open Source Hardware Verification Tools and Frameworks☆625Jan 3, 2026Updated 8 months ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆650Dec 24, 2021Updated 4 years ago
- The PoC Library has been forked to github.com/VHDL/PoC. See new address below☆607Jul 30, 2025Updated last year
- SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)☆74Jan 14, 2021Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Updated this week
- RISC-V SystemC-TLM simulator☆361Feb 20, 2026Updated 7 months ago
- This tool translates synthesizable SystemC code to synthesizable SystemVerilog.☆319Aug 31, 2026Updated 2 weeks ago
- cocotb: Python-based chip (RTL) verification☆2,510Updated this week
- Test suite designed to check compliance with the SystemVerilog standard.☆394Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Constrained random stimuli generation for C++ and SystemC☆54Nov 29, 2023Updated 2 years ago
- Common SystemVerilog components☆799Updated this week
- A modeling library with virtual components for SystemC and TLM simulators☆203Updated this week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆482Jun 10, 2026Updated 3 months ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆19Aug 13, 2018Updated 8 years ago
- A generic class library in SystemVerilog☆91May 20, 2021Updated 5 years ago
- Repurposing existing HDL tools to help writing better code☆227Jun 21, 2026Updated 2 months ago