laurentc2 / FreePDK45_for_KLayout

Related projects ⓘ

Alternatives and complementary repositories for FreePDK45_for_KLayout

• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆38Updated last year
• The-OpenROAD-Project / OpenRCX
  ☆19Updated 3 years ago
• sgherbst / sky130-hello-world
  Minimal SKY130 example with self-checking LVS, DRC, and PEX
  ☆23Updated 3 years ago
• dwarning / VA-Models
  Verilog-A simulation models
  ☆53Updated last week
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆20Updated 5 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated 3 months ago
• bluecheetah / cbag
  A C++ VLSI circuit schematic and layout database library
  ☆13Updated 4 months ago
• johnkustin / bandgapReferenceCircuit
  repository for a bandgap voltage reference in SKY130 technology
  ☆34Updated last year
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 2 years ago
• USCPOSH / AMPSE
  This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…
  ☆24Updated last year
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆37Updated 5 years ago
• mabrains / gdsfactory-generic-pdk
  Generic Process Design Kit for Gdsfactory
  ☆16Updated 6 months ago
• efabless / cace
  Circuit Automatic Characterization Engine
  ☆45Updated last week
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆58Updated 3 weeks ago
• wulffern / aicex
  Files for Advanced Integrated Circuits
  ☆26Updated 3 weeks ago
• ABKGroup / PROBE3.0
  ☆36Updated 7 months ago
• patrickschulz / openPCells
  Parametric layout generator for digital, analog and mixed-signal integrated circuits
  ☆49Updated last week
• OpenTimer / Parser-SPEF
  A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
  ☆51Updated 2 years ago
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• sgherbst / msdsl
  Automatic generation of real number models from analog circuits
  ☆37Updated 7 months ago
• magical-eda / MAGICAL-CIRCUITS
  Circuit release of the MAGICAL project
  ☆29Updated 4 years ago
• AyarLabs / ACG
  Arbitrary Cell Generator enables parametrized grid-free circuit layout creation
  ☆13Updated 4 years ago
• ashwith / pyMOSChar
  Python port of Prof. Boris Murmann's gm/ID Starter Kit
  ☆51Updated 7 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆46Updated 4 years ago
• mabrains / sky130_klayout_pdk
  Skywater 130nm Klayout Device Generators PDK
  ☆29Updated 4 months ago
• chipsalliance / aib-phy-generator
  AIB Generator: Analog hardware compiler for AIB PHY
  ☆30Updated 4 years ago
• niftylab / laygo2
  LAYout with Gridded Objects v2
  ☆52Updated last month
• ucb-art / BAG2_cds_ff_mpt
  BAG2 workspace for fake PDK (cds_ff_mpt)
  ☆54Updated 4 years ago
• RIOSLaboratory / OpenRPDK28
  Open source process design kit for 28nm open process
  ☆45Updated 6 months ago
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆56Updated last month