laurentc2 / ASAP7_for_KLayout

Related projects ⓘ

Alternatives and complementary repositories for ASAP7_for_KLayout

• AUCOHL / Lighter
  An automatic clock gating utility
  ☆43Updated 4 months ago
• bluecheetah / bag
  BAG framework
  ☆41Updated 4 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆35Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆51Updated this week
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• chiselverify / vhdl2verilog
  ☆14Updated 4 years ago
• wulffern / tt06-sar
  SAR ADC on tiny tapeout
  ☆35Updated 2 weeks ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated 10 months ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆39Updated last year
• YosysHQ / padring
  A padring generator for ASICs
  ☆22Updated last year
• ucdrstdenis / cdsAsync
  cdsAsync: An Asynchronous VLSI Toolset & Schematic Library
  ☆25Updated 5 years ago
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆22Updated last year
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆20Updated 3 years ago
• lnis-uofu / TIGFET-10nm-PDK
  An open source PDK using TIGFET 10nm devices.
  ☆43Updated last year
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆46Updated 4 years ago
• semify-eda / fstdumper
  Verilog VPI module to dump FST (Fast Signal Trace) databases
  ☆16Updated last year
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆25Updated 6 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated last year
• snishizawa / libretto
  Characterizer
  ☆21Updated 3 months ago
• pulp-platform / svase
  ☆29Updated 2 months ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆20Updated 5 months ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆40Updated this week
• USCPOSH / AMS_KGD
  A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.
  ☆36Updated 3 years ago
• FPGA-Research-Manchester / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆26Updated 3 years ago
• muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
  This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
  ☆20Updated 5 years ago
• google / globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
  7 track standard cells for GF180MCU provided by GlobalFoundries.
  ☆22Updated last year
• vsdip / vsdStdCellCharacterizer_sky130
  ☆20Updated 3 years ago
• d-m-bailey / cvc
  CVC: Circuit Validity Checker. Check for errors in CDL netlist.
  ☆22Updated last year
• andylithia / Project-Yatsuhashi-Chip1
  ☆39Updated last year