laurentc2 / ASAP7_for_KLayout
KLayout technology files for ASAP7 FinFET educational process
☆20Updated 2 years ago
Alternatives and similar repositories for ASAP7_for_KLayout:
Users that are interested in ASAP7_for_KLayout are comparing it to the libraries listed below
- An automatic clock gating utility☆45Updated 8 months ago
- Characterizer☆21Updated 7 months ago
- ☆36Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- ☆31Updated 2 months ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- A padring generator for ASICs☆25Updated last year
- BAG framework☆40Updated 8 months ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- ☆14Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- A configurable SRAM generator☆47Updated 2 months ago
- Gate-level visualization generator for SKY130-based chip designs.☆19Updated 3 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆40Updated 3 months ago
- Library of open source Process Design Kits (PDKs)☆37Updated last week
- ☆33Updated 2 years ago
- SystemVerilog frontend for Yosys☆81Updated last week
- Analog and power building blocks for sky130 pdk☆20Updated 4 years ago
- A repository for Known Good Designs (KGDs). Does not contain any design files with NDA-sensitive information.☆36Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆46Updated 4 months ago
- ☆10Updated last year
- USB virtual model in C++ for Verilog☆29Updated 5 months ago
- KLayout technology files for Skywater SKY130☆39Updated last year
- LibreSilicon's Standard Cell Library Generator☆18Updated 10 months ago
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆26Updated 3 weeks ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆22Updated 2 months ago
- ☆34Updated this week
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library☆25Updated 5 years ago