laurentc2 / ASAP7_for_KLayoutLinks
KLayout technology files for ASAP7 FinFET educational process
☆21Updated 2 years ago
Alternatives and similar repositories for ASAP7_for_KLayout
Users that are interested in ASAP7_for_KLayout are comparing it to the libraries listed below
Sorting:
- A configurable SRAM generator☆53Updated 3 weeks ago
- An automatic clock gating utility☆50Updated 3 months ago
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- ☆38Updated 3 years ago
- BAG framework☆41Updated last year
- Characterizer☆29Updated 2 months ago
- ☆32Updated 6 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆49Updated 5 years ago
- ☆16Updated 4 years ago
- submission repository for efabless mpw6 shuttle☆30Updated last year
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 4 years ago
- Open source process design kit for 28nm open process☆60Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆45Updated 2 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆8Updated 2 months ago
- https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/☆28Updated 6 months ago
- Trying to verify Verilog/VHDL designs with formal methods and tools☆42Updated last year
- ☆19Updated last year
- Benchmarks for Yosys development☆24Updated 5 years ago
- SAR ADC on tiny tapeout☆42Updated 6 months ago
- Prefix tree adder space exploration library☆57Updated 8 months ago
- ☆18Updated 9 months ago
- Library of open source Process Design Kits (PDKs)☆49Updated last month
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆42Updated 4 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library☆25Updated 3 weeks ago
- Yosys plugin for logic locking and supply-chain security☆22Updated 4 months ago
- ☆47Updated 4 months ago
- CVC: Circuit Validity Checker. Check for errors in CDL netlist.☆23Updated last month