Alternatives and similar repositories for gr-verilog

Users that are interested in gr-verilog are comparing it to the libraries listed below

• Victoromoniyi / gr-litex
  LiteX Accelerator Block for GNU Radio
  ☆24Updated 3 years ago
• gnuradio / gr-verilog
  ☆18Updated 2 years ago
• oscimp / oscimpDigital
  OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing
  ☆58Updated last month
• theseus-cores / theseus-cores
  Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores)
  ☆16Updated 4 years ago
• hamsternz / MMCM_GPSDO
  An all-digital GPS disciplined oscillator using MMCM phase shift.
  ☆31Updated 3 years ago
• ZipCPU / sdr
  A basic Soft(Gate)ware Defined Radio architecture
  ☆99Updated last year
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• newhouseb / alldigitalradio
  All Digital Radio Platform written in nmigen targeting FPGAs (for now)
  ☆81Updated 4 years ago
• noasic / noasic
  An open-source VHDL library for FPGA design.
  ☆32Updated 3 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆31Updated 3 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated 2 years ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆71Updated 4 years ago
• myriadrf / LimeSDR_GW
  LiteX-based gateware for LimeSDR boards.
  ☆15Updated last week
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆46Updated last year
• alpin3 / ulx3s
  Everything needed for ulx3s FPGA
  ☆15Updated 5 years ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆52Updated 2 years ago
• catkira / CIC
  HDL code for a complex multiplier with AXI stream interface
  ☆16Updated 2 years ago
• OpenResearchInstitute / DVB-receiver
  Work being done on the DVB-receiver for Phase 4 Ground.
  ☆59Updated 2 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆66Updated last month
• 360nosc0pe / scope
  Siglent SDS1x0xX-E FPGA bitstreams
  ☆42Updated 10 months ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆35Updated 4 years ago
• HarmonInstruments / verilog
  ☆20Updated 3 years ago
• enjoy-digital / litex-acorn-baseboard
  LiteX development baseboards arround the SQRL Acorn.
  ☆71Updated 8 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆49Updated last month
• lnls-dig / dsp-cores
  Repository containing the DSP gateware cores
  ☆14Updated 2 weeks ago
• emard / flearadio
  Digital FM Radio Receiver for FPGA
  ☆63Updated 9 years ago
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆111Updated 9 years ago
• coralhu123 / KC705-AD9371
  The implementation of AD9371 on KC705
  ☆20Updated 5 months ago
• hdl / constraints
  Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards
  ☆45Updated last week
• srsran / zynq_timestamping
  Open source Zynq timestamping implementation from Software Radio Systems (SRS)
  ☆73Updated 2 years ago