asyncvlsi / act
ACT hardware description language and core tools.
☆107Updated last week
Alternatives and similar repositories for act:
Users that are interested in act are comparing it to the libraries listed below
- Tile based architecture designed for computing efficiency, scalability and generality☆249Updated 3 weeks ago
- Fabric generator and CAD tools☆163Updated last month
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- SystemVerilog synthesis tool☆182Updated 2 weeks ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆144Updated 9 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆268Updated last week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆133Updated 6 months ago
- Logic synthesis and ABC based optimization☆49Updated 2 weeks ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆102Updated 4 months ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V☆169Updated this week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆212Updated last week
- FPGA Assembly (FASM) Parser and Generator☆91Updated 2 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆138Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 10 months ago
- high-performance RTL simulator☆153Updated 9 months ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆170Updated 8 months ago
- ☆139Updated 2 weeks ago
- magma circuits☆259Updated 5 months ago
- ☆102Updated 2 years ago
- A dynamic verification library for Chisel.☆147Updated 4 months ago
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆88Updated last year
- A Fast, Low-Overhead On-chip Network☆184Updated this week
- SystemVerilog frontend for Yosys☆81Updated last week
- A complete open-source design-for-testing (DFT) Solution☆146Updated 4 months ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆166Updated 5 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Top-level repository for the ACT EDA flow☆27Updated last week
- Mutation Cover with Yosys (MCY)☆80Updated 2 weeks ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆119Updated 9 months ago