asyncvlsi / actLinks
ACT hardware description language and core tools.
☆122Updated this week
Alternatives and similar repositories for act
Users that are interested in act are comparing it to the libraries listed below
Sorting:
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆120Updated 2 years ago
- Open-source FPGA research and prototyping framework.☆210Updated last year
- WAL enables programmable waveform analysis.☆162Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- SystemVerilog frontend for Yosys☆178Updated this week
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆229Updated this week
- SystemVerilog synthesis tool☆220Updated 9 months ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆144Updated 2 years ago
- An automatic clock gating utility☆51Updated 7 months ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆180Updated 7 months ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆307Updated 2 months ago
- Mutation Cover with Yosys (MCY)☆88Updated last week
- Open Application-Specific Instruction Set processor tools (OpenASIP)☆168Updated this week
- ☆33Updated 11 months ago
- Fabric generator and CAD tools.☆209Updated this week
- Tile based architecture designed for computing efficiency, scalability and generality☆276Updated 2 months ago
- ☆58Updated 8 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆238Updated 3 months ago
- ☆104Updated 3 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- FPGA tool performance profiling☆103Updated last year
- RISC-V Formal Verification Framework☆169Updated last week
- BAG framework☆41Updated last year
- A complete open-source design-for-testing (DFT) Solution☆171Updated 3 months ago
- Main page☆128Updated 5 years ago
- Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.☆116Updated 7 months ago