asyncvlsi / actLinks
ACT hardware description language and core tools.
☆121Updated last week
Alternatives and similar repositories for act
Users that are interested in act are comparing it to the libraries listed below
Sorting:
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆118Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated last year
- Open-source FPGA research and prototyping framework.☆209Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆161Updated last month
- SystemVerilog frontend for Yosys☆168Updated last week
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation☆226Updated this week
- SystemVerilog synthesis tool☆216Updated 8 months ago
- Mutation Cover with Yosys (MCY)☆88Updated 3 weeks ago
- An automatic clock gating utility☆51Updated 6 months ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆237Updated 2 months ago
- ☆33Updated 10 months ago
- ☆104Updated 3 years ago
- FPGA tool performance profiling☆102Updated last year
- SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA☆142Updated 2 years ago
- WAL enables programmable waveform analysis.☆160Updated 2 weeks ago
- Fabric generator and CAD tools.☆203Updated this week
- For contributions of Chisel IP to the chisel community.☆67Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆116Updated 4 years ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆300Updated 3 weeks ago
- Structural Netlist API (and more) for EDA post synthesis flow development☆120Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 6 months ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- A SystemVerilog source file pickler.☆60Updated last year
- Tile based architecture designed for computing efficiency, scalability and generality☆272Updated last month
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- RISC-V Formal Verification Framework☆162Updated 2 weeks ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- Generic Register Interface (contains various adapters)☆132Updated 3 weeks ago
- ☆58Updated 7 months ago