Alternatives and similar repositories for act:

Users that are interested in act are comparing it to the libraries listed below

• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆265Updated this week
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆177Updated this week
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆141Updated 8 months ago
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆49Updated last week
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆209Updated 3 months ago
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆161Updated 4 years ago
• rdaly525 / coreir
  ☆102Updated 2 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools
  ☆160Updated last week
• circuitgraph / circuitgraph
  Tools for working with circuits as graphs in python
  ☆111Updated last year
• efabless / chipignite-resources
  ☆79Updated 2 years ago
• chipsalliance / aib-phy-hardware
  Advanced Interface Bus (AIB) die-to-die hardware open source
  ☆132Updated 5 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆54Updated 4 months ago
• ncsu-eda / FreePDK3
  ☆133Updated 3 years ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 9 months ago
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆145Updated 3 months ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆146Updated last week
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• ucsc-vama / essent
  high-performance RTL simulator
  ☆152Updated 8 months ago
• mflowgen / mflowgen
  mflowgen -- A Modular ASIC/FPGA Flow Generator
  ☆247Updated 3 weeks ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆244Updated last week
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆146Updated 3 months ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆86Updated 2 years ago
• efabless / mpw_precheck
  ☆36Updated 2 weeks ago
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆102Updated 3 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆109Updated 3 years ago
• phanrahan / magma
  magma circuits
  ☆255Updated 4 months ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆171Updated last week