Alternatives and similar repositories for act

Users that are interested in act are comparing it to the libraries listed below

• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆210Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆119Updated 2 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆162Updated 2 weeks ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆218Updated 8 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆172Updated this week
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆179Updated 6 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆166Updated 3 weeks ago
• rdaly525 / coreir
  ☆104Updated 3 years ago
• BSVLang / Main
  Main page
  ☆128Updated 5 years ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆208Updated last week
• lnis-uofu / SOFA
  SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
  ☆144Updated 2 years ago
• masc-ucsc / livehd
  Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation
  ☆229Updated this week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆88Updated 2 weeks ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆161Updated 2 weeks ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆274Updated 2 months ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 5 years ago
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆116Updated 6 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 7 months ago
• ucb-bar / hammer
  Hammer: Highly Agile Masks Made Effortlessly from RTL
  ☆303Updated last month
• pulp-platform / svase
  ☆33Updated 10 months ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 2 months ago
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆83Updated last year
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆103Updated last year
• cpc / openasip
  Open Application-Specific Instruction Set processor tools (OpenASIP)
  ☆168Updated last month
• phanrahan / magma
  magma circuits
  ☆263Updated last year
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆136Updated 3 years ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 8 months ago