RTimothyEdwards / irsimLinks
IRSIM switch-level simulator for digital circuits
☆35Updated 2 months ago
Alternatives and similar repositories for irsim
Users that are interested in irsim are comparing it to the libraries listed below
Sorting:
- Benchmarks for Yosys development☆24Updated 5 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated last month
- ☆33Updated 3 years ago
- A Verilog Synthesis Regression Test☆37Updated 2 weeks ago
- PicoRV☆43Updated 5 years ago
- Coriolis VLSI EDA Tool (LIP6)☆77Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 4 years ago
- LunaPnR is a place and router for integrated circuits☆47Updated 6 months ago
- Bitstream relocation and manipulation tool.☆50Updated 3 years ago
- Small footprint and configurable Inter-Chip communication cores☆66Updated 2 weeks ago
- RISC-V Processor written in Amaranth HDL☆39Updated 4 years ago
- Demo SoC for SiliconCompiler.☆62Updated this week
- KLayout technology files for ASAP7 FinFET educational process☆24Updated 2 years ago
- ☆20Updated 5 years ago
- ☆38Updated 3 years ago
- USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL☆32Updated last year
- Custom IC Creator (ciccreator) is a compiler that takes in a object definition file (JSON), a SPICE file, and a design rule file and outp…☆35Updated 7 months ago
- Qrouter detail router for digital ASIC designs☆57Updated 2 months ago
- A collection of big designs to run post-synthesis simulations with yosys☆51Updated 10 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆110Updated last week
- mantle library☆44Updated 3 years ago
- Gate-level visualization generator for SKY130-based chip designs.☆21Updated 4 years ago
- Featherweight RISC-V implementation☆53Updated 4 years ago
- ☆38Updated 3 years ago
- Digital Circuit rendering engine☆39Updated 6 months ago
- Translates GDSII into HTML/JS that can be viewed in WebGL-capable web browsers.☆59Updated 5 years ago
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- ✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.☆38Updated last week