Alternatives and similar repositories for irsim

Users that are interested in irsim are comparing it to the libraries listed below

• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆20Updated 2 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated last month
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 2 months ago
• asinghani / sky130-chip-vis
  Gate-level visualization generator for SKY130-based chip designs.
  ☆19Updated 3 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• RTimothyEdwards / qrouter
  Qrouter detail router for digital ASIC designs
  ☆57Updated last month
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆58Updated last week
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆28Updated 3 weeks ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆27Updated 2 years ago
• htfab / rotfpga
  A reconfigurable logic circuit made of identical rotatable tiles.
  ☆21Updated 3 years ago
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• clairexen / picorv
  PicoRV
  ☆44Updated 5 years ago
• shalan / Awesome-Sky130-IPs
  ☆10Updated last year
• drom / logidrom
  Digital Circuit rendering engine
  ☆39Updated last year
• veripool / dinotrace
  Simulation VCD waveform viewer, using old Motif UI
  ☆26Updated 2 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆43Updated 3 months ago
• 0x01be / rudder
  Learn, share and collaborate on ASIC design using open tools and technologies
  ☆13Updated 4 years ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated 5 months ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• asicsforthemasses / LunaPnR
  LunaPnR is a place and router for integrated circuits
  ☆46Updated 6 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated 3 weeks ago
• SymbioticEDA / getting-started-FV
  ☆18Updated 4 years ago
• siliconcompiler / logiklib
  Library of FPGA architectures
  ☆21Updated 2 months ago
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago