aolofsson / POSHLinks
☆44Updated 5 years ago
Alternatives and similar repositories for POSH
Users that are interested in POSH are comparing it to the libraries listed below
Sorting:
- ☆33Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆49Updated 6 months ago
- Open source process design kit for 28nm open process☆56Updated last year
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- ☆20Updated 3 years ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated this week
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- A configurable SRAM generator☆50Updated last week
- SKY130 SRAM macros generated by SRAM 22☆16Updated last month
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆27Updated 4 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Open source RTL simulation acceleration on commodity hardware☆27Updated 2 years ago
- Material for OpenROAD Tutorial at DAC 2020☆47Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆35Updated last week
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆22Updated 5 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 2 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Open Source PHY v2☆28Updated last year
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- Library of open source Process Design Kits (PDKs)☆42Updated last week
- An automatic clock gating utility☆47Updated last month
- ☆31Updated last year
- ☆32Updated 4 months ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆65Updated 3 months ago
- Intel's Analog Detailed Router☆38Updated 5 years ago
- Mirror of Synopsys's Liberty parser library☆21Updated 6 years ago
- Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)☆38Updated last week
- sram/rram/mram.. compiler☆35Updated last year