aolofsson / POSHLinks
☆44Updated 5 years ago
Alternatives and similar repositories for POSH
Users that are interested in POSH are comparing it to the libraries listed below
Sorting:
- ☆33Updated 5 years ago
- Open source process design kit for 28nm open process☆61Updated last year
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 9 months ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- AMC: Asynchronous Memory Compiler☆50Updated 5 years ago
- Library of open source Process Design Kits (PDKs)☆51Updated this week
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- ☆20Updated 3 years ago
- A configurable SRAM generator☆54Updated 3 weeks ago
- Open Source PHY v2☆30Updated last year
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 6 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆19Updated 5 years ago
- ☆32Updated 8 months ago
- SKY130 SRAM macros generated by SRAM 22☆16Updated 3 weeks ago
- sram/rram/mram.. compiler☆40Updated 2 years ago
- Intel's Analog Detailed Router☆39Updated 6 years ago
- Automatic generation of real number models from analog circuits☆43Updated last year
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆43Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆86Updated 11 months ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats☆47Updated 4 years ago
- ☆67Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- Builds, flow and designs for the alpha release☆54Updated 5 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- ☆31Updated last year
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 6 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆38Updated 2 months ago