☆44Jan 26, 2020Updated 6 years ago
Alternatives and similar repositories for POSH
Users that are interested in POSH are comparing it to the libraries listed below
Sorting:
- ☆33Jan 24, 2020Updated 6 years ago
- Circuit release of the MAGICAL project☆40Jan 10, 2020Updated 6 years ago
- A C++ VLSI circuit schematic and layout database library☆15Jul 1, 2024Updated last year
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 6 years ago
- DATC Robust Design Flow.☆35Jan 21, 2020Updated 6 years ago
- EDA physical synthesis optimization kit☆64Nov 13, 2023Updated 2 years ago
- GUI for SymbiYosys☆17Oct 13, 2025Updated 4 months ago
- Designs for Process-Voltage-Temperature (PVT) Sensors with MCU☆24May 8, 2020Updated 5 years ago
- LibreSilicon's Standard Cell Library Generator☆22Oct 30, 2025Updated 4 months ago
- tools regarding on analog modeling, validation, and generation☆22Apr 11, 2023Updated 2 years ago
- AMC: Asynchronous Memory Compiler☆53Jun 29, 2020Updated 5 years ago
- This is the repository of IPs of the group in USC who is developing Analog Mixed-signal Parameter Search Engine (AMPSE). You can download…☆25Mar 11, 2023Updated 2 years ago
- ☆14Aug 27, 2020Updated 5 years ago
- Copyleftist's Standard Cell Library☆101May 2, 2024Updated last year
- IDEA project source files☆111Oct 15, 2025Updated 4 months ago
- ☆38Dec 29, 2022Updated 3 years ago
- ☆339Jan 13, 2026Updated last month
- Object-Oriented Programming☆12Aug 26, 2021Updated 4 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆18Dec 5, 2022Updated 3 years ago
- ☆109Dec 5, 2019Updated 6 years ago
- Delay Calculation ToolKit☆32Aug 7, 2022Updated 3 years ago
- GDSII File Parsing, IC Layout Analysis, and Parameter Extraction☆129Apr 23, 2023Updated 2 years ago
- Coriolis VLSI EDA Tool (LIP6)☆81Jan 25, 2026Updated last month
- OpenDesign Flow Database☆17Oct 31, 2018Updated 7 years ago
- Custom IC Creator Simulation tools☆22Dec 29, 2025Updated 2 months ago
- 12 bit SAR ADC IP in Skywater 130 nm PDK☆24May 30, 2024Updated last year
- ☆32Dec 16, 2021Updated 4 years ago
- Machine Generated Analog IC Layout☆271Apr 24, 2024Updated last year
- ☆59Jul 11, 2025Updated 7 months ago
- Open design rule (1um)☆22Oct 18, 2022Updated 3 years ago
- ☆19Oct 28, 2024Updated last year
- SMT-based-STDCELL-Layout-Generator☆18Sep 30, 2021Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Feb 18, 2020Updated 6 years ago
- ☆20Mar 1, 2021Updated 5 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆37Dec 30, 2022Updated 3 years ago
- Dr. CU, VLSI Detailed Routing Tool Developed by CUHK☆142Mar 20, 2023Updated 2 years ago
- Synchronous FIFOs designed in Verilog/System Verilog.☆25Dec 21, 2025Updated 2 months ago
- ☆20Nov 22, 2021Updated 4 years ago
- Open source process design kit for 28nm open process☆72Apr 23, 2024Updated last year