bsg-idea / uw_openroad_free45Links
UW reference flow for Free45PDK and The OpenROAD Project
☆12Updated 5 years ago
Alternatives and similar repositories for uw_openroad_free45
Users that are interested in uw_openroad_free45 are comparing it to the libraries listed below
Sorting:
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- ☆43Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- Introductory course into static timing analysis (STA).☆99Updated 5 months ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆46Updated 5 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Reed Solomon Decoder (204,188)☆12Updated 11 years ago
- Python Tool for UVM Testbench Generation☆55Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 11 months ago
- A simple DDR3 memory controller☆61Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆73Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆56Updated 5 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 3 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- SystemVerilog modules and classes commonly used for verification☆52Updated 3 weeks ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆37Updated 3 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆23Updated 3 years ago
- ☆183Updated 4 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated last month
- Static Timing Analysis Full Course☆63Updated 2 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆28Updated 4 years ago
- A free standard cell library for SDDS-NCL circuits☆28Updated 2 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆60Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- A complete open-source design-for-testing (DFT) Solution☆173Updated 3 months ago
- This is a tutorial on standard digital design flow☆80Updated 4 years ago
- ☆110Updated last month
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆143Updated last week