bsg-idea / uw_openroad_free45Links
UW reference flow for Free45PDK and The OpenROAD Project
☆11Updated 5 years ago
Alternatives and similar repositories for uw_openroad_free45
Users that are interested in uw_openroad_free45 are comparing it to the libraries listed below
Sorting:
- ☆42Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆78Updated 4 years ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 8 months ago
- Reed Solomon Decoder (204,188)☆12Updated 11 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 9 months ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- ☆97Updated 2 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆64Updated 4 years ago
- AMC: Asynchronous Memory Compiler☆51Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆70Updated 4 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆74Updated 4 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Python Tool for UVM Testbench Generation☆54Updated last year
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆175Updated 10 months ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- Simple single-port AXI memory interface☆46Updated last year
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- Introductory course into static timing analysis (STA).☆97Updated 2 months ago
- ☆25Updated last year
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆110Updated 4 years ago
- round robin arbiter☆75Updated 11 years ago
- This is a tutorial on standard digital design flow☆79Updated 4 years ago
- A complete open-source design-for-testing (DFT) Solution☆164Updated 3 weeks ago
- A simple DDR3 memory controller☆59Updated 2 years ago
- ideas and eda software for vlsi design☆50Updated last month
- Standard Cell Library based Memory Compiler using FF/Latch cells☆158Updated 2 months ago