Alternatives and similar repositories for arv:

Users that are interested in arv are comparing it to the libraries listed below

• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 4 years ago
• rsnikhil / RISCV_ISA_Formal_Spec_in_BSV
  A formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
  ☆20Updated 7 years ago
• rsnikhil / RISCV_ISA_Spec_Tour
  Tutorial tour of the RISC-V ISA Spec (expressed in SAIL ISA spec language)
  ☆36Updated 4 years ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆35Updated last month
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• marlls1989 / pulsar
  Pulsar asynchronous synthesis framework
  ☆11Updated 4 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last week
• tvanas / r-vex
  A reconfigurable and extensible VLIW processor implemented in VHDL
  ☆32Updated 10 years ago
• B-Lang-org / bdw
  BSC Development Workstation (BDW)
  ☆28Updated 5 months ago
• cliffordwolf / xbitmanip
  RISC-V XBitmanip Extension
  ☆27Updated 6 years ago
• efabless / proton
  ☆31Updated 4 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆33Updated 8 years ago
• riadhbenabdelhamid / BRISKI
  BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …
  ☆19Updated this week
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆47Updated last week
• tomverbeure / mr1
  MR1 formally verified RISC-V CPU
  ☆54Updated 6 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• CTSRD-CHERI / BlueStuff
  A Bluespec SystemVerilog library of miscellaneous components
  ☆16Updated last week
• jrmoserbaltimore / risc-v-cpu-asynchronous
  A RISC-V CPU implementation
  ☆12Updated 5 years ago
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 5 years ago
• jerry-D / SYMPL-GP-GPU-Compute-Engines
  Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…
  ☆22Updated 6 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• openrisc / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆32Updated 3 years ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 7 years ago
• foshardware / lsc
  Libre Silicon Compiler
  ☆23Updated 4 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago