Alternatives and similar repositories for hackt

Users that are interested in hackt are comparing it to the libraries listed below

• pulp-platform / svase
  ☆33Updated last year
• rdaly525 / coreir
  ☆104Updated 3 years ago
• The-OpenROAD-Project / alpha-release
  Builds, flow and designs for the alpha release
  ☆54Updated 6 years ago
• benjmarshall / hlsclt
  A Vivado HLS Command Line Helper Tool
  ☆36Updated 4 years ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆60Updated last year
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆51Updated 9 months ago
• chipsalliance / UHDM-integration-tests
  ☆31Updated 2 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆51Updated 5 years ago
• leonardt / fault
  A Python package for testing hardware (part of the magma ecosystem)
  ☆47Updated last year
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆89Updated this week
• Xilinx / XilinxUnisimLibrary
  Xilinx Unisim Library in Verilog
  ☆86Updated 5 years ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆121Updated last week
• tdene / synth_opt_adders
  Prefix tree adder space exploration library
  ☆56Updated last year
• Intuity / nexus
  Open source RTL simulation acceleration on commodity hardware
  ☆33Updated 2 years ago
• Kuree / hgdb
  Hardware generator debugger
  ☆77Updated last year
• broccolimicro / loom
  design and verification of asynchronous circuits
  ☆42Updated 3 weeks ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆44Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆59Updated 3 years ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆38Updated 3 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆57Updated 4 months ago
• manish-kj / PACoGen
  PACoGen: Posit Arithmetic Core Generator
  ☆76Updated 6 years ago
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆92Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆120Updated 2 years ago
• pulp-platform / cheshire-ihp130-o
  ☆58Updated 9 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆186Updated last week
• ymherklotz / verismith
  Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
  ☆119Updated 8 months ago
• efabless / sky130_sram_macros_old
  ☆38Updated 3 years ago
• fabianschuiki / potstill
  An open source generator for standard cell based memories.
  ☆14Updated 9 years ago