asyncvlsi / actflow
Top-level repository for the ACT EDA flow
☆26Updated this week
Alternatives and similar repositories for actflow:
Users that are interested in actflow are comparing it to the libraries listed below
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆44Updated last week
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆23Updated 7 months ago
- BAG framework☆40Updated 5 months ago
- AMC: Asynchronous Memory Compiler☆47Updated 4 years ago
- cdsAsync: An Asynchronous QDI VLSI Toolset & Schematic Library☆25Updated 5 years ago
- A configurable SRAM generator☆42Updated last week
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆64Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- An open source generator for standard cell based memories.☆12Updated 8 years ago
- ☆24Updated this week
- ☆36Updated 2 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 4 years ago
- Open source process design kit for 28nm open process☆46Updated 8 months ago
- ☆31Updated 2 weeks ago
- Verilog-A simulation models☆63Updated last week
- sram/rram/mram.. compiler☆30Updated last year
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆39Updated 6 months ago
- SystemVerilog frontend for Yosys☆68Updated last week
- Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license☆38Updated 5 months ago
- ☆36Updated 3 months ago
- Hardware Description Library☆71Updated last month
- AIB Generator: Analog hardware compiler for AIB PHY☆30Updated 4 years ago
- ☆45Updated last month
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 8 months ago
- KLayout technology files for Skywater SKY130☆39Updated last year
- An automatic clock gating utility☆43Updated 6 months ago
- ☆78Updated 2 years ago
- ☆40Updated 4 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆33Updated 2 months ago
- ACT hardware description language and core tools.☆105Updated this week