Alternatives and similar repositories for pulsar

Users that are interested in pulsar are comparing it to the libraries listed below

• AUCOHL / Lighter
  An automatic clock gating utility
  ☆50Updated 3 months ago
• pulp-platform / svase
  ☆32Updated 6 months ago
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆135Updated last week
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆114Updated last week
• spider-tronix / Standard-Cell-Characterization
  Open Source tool to build liberty files and for Characterizing Standard Cells.
  ☆27Updated 4 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆49Updated 5 years ago
• pulp-platform / cheshire-ihp130-o
  ☆47Updated 3 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆201Updated 4 months ago
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated last week
• efabless / sky130_sram_macros_old
  ☆37Updated 3 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 3 years ago
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆151Updated last week
• AUCOHL / Fault
  A complete open-source design-for-testing (DFT) Solution
  ☆161Updated last month
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆68Updated last week
• rsnikhil / Bluespec_BSV_Tutorial
  Bluespec BSV HLHDL tutorial
  ☆105Updated 9 years ago
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆115Updated last year
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆59Updated 8 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆85Updated last year
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆95Updated last week
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆88Updated last year
• laurentc2 / ASAP7_for_KLayout
  KLayout technology files for ASAP7 FinFET educational process
  ☆21Updated 2 years ago
• rahulk29 / sram22
  A configurable SRAM generator
  ☆53Updated last week
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆137Updated 3 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆70Updated 4 years ago
• tdb-alcorn / chisel-formal
  ☆23Updated 4 years ago
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆155Updated last month
• BSVLang / Main
  Main page
  ☆126Updated 5 years ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆142Updated last month
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆35Updated last week
• efabless / chipignite-resources
  ☆79Updated 2 years ago