ARCH hardware description language and compiler
☆48Jul 14, 2026Updated this week
Alternatives and similar repositories for arch-com
Users that are interested in arch-com are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Expose what functional RTL benchmarks leave unanswered. Evidence profiles for AI-generated RTL; research collaborators and design partner…☆15Updated this week
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 4 months ago
- This repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primar…☆42Mar 28, 2022Updated 4 years ago
- CoreSmith is a Prompt to GDS Agentic Flow☆30Jun 2, 2026Updated last month
- ☆21Updated this week
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This repository contains sample code integrating Renode with Verilator☆27May 27, 2025Updated last year
- ☆36Jun 25, 2026Updated 2 weeks ago
- Netlist API (and more) for EDA flow development☆149Updated this week
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆25Jan 24, 2026Updated 5 months ago
- VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation deb…☆39Nov 6, 2025Updated 8 months ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆45Apr 13, 2023Updated 3 years ago
- Minimal TPU implementation with 8x8 systolic array and PyTorch integration☆64Jan 26, 2026Updated 5 months ago
- Debug waveforms with GDB☆33Nov 12, 2025Updated 8 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Catalyst N1 — Open source neuromorphic processor (Loihi 1 parity). 128 cores, 131K neurons, 14-opcode learning ISA, FPGA-validated on AWS…☆38Jun 2, 2026Updated last month
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆18Updated this week
- Scalable Interface for RISC-V ISA Extensions☆26Jun 9, 2026Updated last month
- Filelist generator☆21Jun 23, 2026Updated 3 weeks ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆107Jul 1, 2026Updated last week
- Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing viola…☆19Oct 4, 2022Updated 3 years ago
- Elite Statements of Purpose (SOPs), Academic CVs, Motivation Letters, and Research Proposals from successful global scholarship applicant…☆70Jun 16, 2026Updated 3 weeks ago
- ☆21May 8, 2025Updated last year
- ☆190Jun 8, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Helper package to spin-up a Qdrant instance without Docker☆13Dec 24, 2023Updated 2 years ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 11 months ago
- ☆42Dec 21, 2025Updated 6 months ago
- SystemVerilog (IEEE 1800-2017) Simulator☆60Updated this week
- Digital HDL Design Full-stack Agents☆165Updated this week
- A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.☆79Apr 30, 2026Updated 2 months ago
- Convert an image to a GDS format for inclusion in a zerotoasic project☆19Jun 16, 2022Updated 4 years ago
- ☆36Apr 22, 2026Updated 2 months ago
- Algorithm to hardware compilation tools (e.g. C to VHDL).☆45Nov 30, 2025Updated 7 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- [NeurIPS 2024 Spotlight] Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs☆15Feb 22, 2026Updated 4 months ago
- few python scripts to clone all IP cores from opencores.org☆29Jan 8, 2024Updated 2 years ago
- tools regarding on analog modeling, validation, and generation☆25Apr 11, 2023Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Feb 25, 2023Updated 3 years ago
- An interactive digital logic simulator with verilog support (Yosys)☆28Apr 2, 2026Updated 3 months ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆31Updated this week
- Awesome projects using the Amaranth HDL☆20Feb 6, 2025Updated last year