ARCH hardware description language and compiler
☆73Aug 3, 2026Updated this week
Alternatives and similar repositories for arch-com
Users that are interested in arch-com are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Digital Design Equivalence Checking☆89Updated this week
- Expose what functional RTL benchmarks leave unanswered. Evidence profiles for AI-generated RTL; research collaborators and design partner…☆18Jul 22, 2026Updated last week
- RTLMeter benchmark suite☆31Jul 21, 2026Updated last week
- Digital logic benchmark suite☆77Jul 27, 2026Updated last week
- ☆21Jul 22, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- CoreSmith is a Prompt to GDS Agentic Flow☆34Updated this week
- The first large scale formally verified reasoning dataset for Verilog☆22May 16, 2025Updated last year
- Catalyst N1 — Open source neuromorphic processor (Loihi 1 parity). 128 cores, 131K neurons, 14-opcode learning ISA, FPGA-validated on AWS…☆40Jun 2, 2026Updated 2 months ago
- SystemVerilog file list pruner☆18Updated this week
- A tool for cross-checking Verilog compilers☆15Apr 16, 2025Updated last year
- ☆42Dec 21, 2025Updated 7 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆45Apr 13, 2023Updated 3 years ago
- This repository contains sample code integrating Renode with Verilator☆27May 27, 2025Updated last year
- ☆18Feb 25, 2026Updated 5 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Self-contained RTL to GDS flow for simple chip designs☆73Jul 7, 2026Updated 3 weeks ago
- Netlist API (and more) for EDA flow development☆155Updated this week
- Custom IC Design Platform☆112Updated this week
- Agile Hardware Design Course☆15Nov 17, 2025Updated 8 months ago
- Open-source RTL logic simulator with CUDA acceleration☆289Sep 30, 2025Updated 10 months ago
- ☆32Jun 15, 2026Updated last month
- Debug waveforms with GDB☆33Nov 12, 2025Updated 8 months ago
- ☆24Updated this week
- ☆19Nov 1, 2025Updated 9 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- RISC-V Dual-Issue RV32I Core in SystemVerilog☆19Jun 26, 2026Updated last month
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 3 months ago
- ☆16Aug 26, 2025Updated 11 months ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆21Sep 10, 2025Updated 10 months ago
- A collection of datapath circuit design and verification benchmarks☆19Jul 9, 2026Updated 3 weeks ago
- A verilog hardware description model of LLM for FPGA / SoC - runs newest LLM models☆27Jan 24, 2026Updated 6 months ago
- ☆21May 8, 2025Updated last year
- Lightweight Neural Architecture Search for Temporal Convolutional Networks at the Edge☆10Mar 6, 2023Updated 3 years ago
- ☆198Jun 8, 2026Updated last month
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This repo contains the skeleton scripts for running a full RTL2GDS flow using Cadence tools, as demonstrated in the Full RTL2GDS Demo pre…☆83Oct 18, 2025Updated 9 months ago
- ☆33Nov 2, 2025Updated 9 months ago
- Kicad schematics and PCB layout for an 8 channel ADSR based on CEM3310/AS3310☆13Nov 6, 2021Updated 4 years ago
- Fabric generator and CAD tools graphical frontend☆18Aug 5, 2025Updated 11 months ago
- This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Pyt…☆28Feb 16, 2026Updated 5 months ago
- Hack@DAC 2021☆20Jul 24, 2024Updated 2 years ago
- This repository contains 4000 vulnerable hardware designs. Currently this is in Jsonl format for directly using it for fine-tuning LLMs. …☆24Mar 25, 2025Updated last year