Alternatives and similar repositories for SVALint

Users that are interested in SVALint are comparing it to the libraries listed below

• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆20Updated 6 months ago
• openhwgroup / cvw-arch-verif
  The purpose of the repo is to support CORE-V Wally architectural verification
  ☆12Updated this week
• Corey-Maler / simple_SoC
  Small and simple, primitive SoC with GPU, CPU, RAM, GPIO
  ☆13Updated 8 years ago
• zeroasiccorp / ebrick-demo
  Demo: how to create a custom EBRICK
  ☆21Updated 6 months ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 5 years ago
• KiranThomasCherian / VLSI-and-Computer-Architecture
  Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim
  ☆13Updated 4 years ago
• TinyTapeout / tt10-verilog-template
  Submission template for Tiny Tapeout 10 - Verilog HDL Projects
  ☆21Updated 3 months ago
• nayiri-k / fsdb-parse
  Parse FSDB waveform files
  ☆15Updated last year
• haile1713 / Simple--Expense-tracker-app-with-ML-
  A feature-rich expense tracker app that allows users to log, categorize, and track expenses. Customize it with AI/ML for project expense …
  ☆8Updated 7 months ago
• The-OpenROAD-Project / megaboom
  ☆25Updated this week
• TinyTapeout / tt-support-tools
  tools used by project repos to test configuration, generate OpenLane run summaries and documentation
  ☆21Updated this week
• buyi-Yang / getQzonehistory
  ☆11Updated 6 months ago
• tiremoscode / dw-grupo58
  ☆20Updated 6 months ago
• Shoaib001001 / Module---Machine-Learning-Algorithm-s-
  ☆9Updated 8 months ago
• AmjadAziz98 / BanoQabil_Python
  In this repository, we delve into the basic concepts of python from scratch. We explored every thing from a beginner perscpective who sta…
  ☆8Updated 8 months ago
• shalan / Awesome-Sky130-IPs
  ☆10Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆41Updated 2 years ago
• pulp-platform / axi_node
  AXI X-Bar
  ☆19Updated 5 years ago
• adrianymeri / Bazat-E-Programimit-2024
  ☆7Updated 5 months ago
• abduvalimurodullayev1 / BookApi
  This is web api for book site
  ☆9Updated 7 months ago
• zli87 / Integrated_Circuit_Design_Laboratory_IC_Lab
  Integrated Circuit Design Laboratory(IC Lab) at 2019 Fall, NCTU. Final project is a customized 16 bits ISA processor.
  ☆23Updated 3 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated last year
• EliasEsperanza / UES-API
  API de mapeo para la Universidad de El Salvador (UES), desarrollada por estudiantes de la Facultad Multidisciplinaria Oriental. Proporcio…
  ☆16Updated 6 months ago
• AnkitChemjong / Quiz-App
  ☆9Updated 9 months ago
• PacoReinaCampo / vhdl2verilog
  Hardware Description Language Translator
  ☆16Updated last week
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated 3 weeks ago
• WilliamRaoF / CPP_POO_GTECH
  ☆6Updated 6 months ago
• Intelligent-Computing-Research-Group / HaVen
  [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers
  ☆18Updated this week
• pulp-platform / chimera
  ☆16Updated 3 weeks ago
• a2k-hanlon / linter-veriloghdl
  Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.
  ☆10Updated last year