Catalyst N1 — Open source neuromorphic processor (Loihi 1 parity). 128 cores, 131K neurons, 14-opcode learning ISA, FPGA-validated on AWS F2.
☆39Jun 2, 2026Updated last month
Alternatives and similar repositories for catalyst-n1
Users that are interested in catalyst-n1 are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- SystemVerilog file list pruner☆18Mar 2, 2026Updated 4 months ago
- RTL implementation of a performance/area optimized bfloat16 adder and multiplication.☆29Mar 28, 2026Updated 4 months ago
- A minimal neuromorphic chip design in SystemVerilog to learn how brain-inspired computing works from the ground up.☆29Mar 30, 2026Updated 3 months ago
- End-to-End Open-Source I2C GPIO Expander☆45Updated this week
- 3-wide superscalar, out-of-order RISC-V processor (RV32IM subset) in System Verilog, demonstrating key Instruction-Level Parallelism☆31Aug 15, 2025Updated 11 months ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ARCH hardware description language and compiler☆51Updated this week
- This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Pyt…☆28Feb 16, 2026Updated 5 months ago
- HTB_Write_Ups☆27Feb 25, 2024Updated 2 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆21Oct 22, 2025Updated 9 months ago
- ☆28Jan 31, 2021Updated 5 years ago
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆34May 4, 2025Updated last year
- ☆11Jun 10, 2015Updated 11 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆23Nov 9, 2025Updated 8 months ago
- IPASS -- Image Processing Algorithm Simulation Software☆11Jul 25, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆34Feb 2, 2026Updated 5 months ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, A…☆47Nov 8, 2023Updated 2 years ago
- Library with VHDL cores implementing Advanced Microcontroller Bus Architecture 5 (AMBA5) specifications such as APB, AHB, AXI, and AXI-St…☆18Jun 20, 2026Updated last month
- Example of how to use UVM with Verilator☆46Apr 20, 2026Updated 3 months ago
- IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator tape…☆40Jul 10, 2026Updated 2 weeks ago
- Architecting and Building High Speed SoCs, published by Packt☆31Jan 18, 2023Updated 3 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆88Oct 6, 2022Updated 3 years ago
- ☆13Jul 20, 2026Updated last week
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop☆44Jun 6, 2021Updated 5 years ago
- Baseband Receiver IP for GPS like DSSS signals☆43May 19, 2020Updated 6 years ago
- verilog实现CLAHE（限制对比度自适应直方图均衡化）算法，并进行资源优化，含vivado综合工程。 // Verilog implementation of CLAHE (Contrast Limited Adaptive Histogram…☆20Apr 30, 2026Updated 2 months ago
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- This project is about building a high FOM 2.4 GHz LNA for Bluetooth Low-Energy (BLE) Standards, using 45nm CMOS technology.☆16Mar 17, 2019Updated 7 years ago
- ☆32Jun 18, 2026Updated last month
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆121Jun 18, 2026Updated last month
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆18Updated this week
- ☆49Apr 7, 2024Updated 2 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆21Aug 10, 2023Updated 2 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆107Jul 1, 2026Updated 3 weeks ago
- DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep lea…☆22Aug 13, 2025Updated 11 months ago
- A design automation framework to engineer decision diagrams yourself☆27Jul 19, 2026Updated last week
- A 5-stage pipelined, rv32i core with branch prediction and hazard detection☆15Dec 11, 2025Updated 7 months ago
- A customized copy of OpenOCD able to access the jtagd/jtagserver distributed with Quartus. At present it is restricted to accessing the A…☆12Aug 18, 2025Updated 11 months ago
- Verilog Implementation of Otsu's algorithm☆14Jan 18, 2020Updated 6 years ago