CoreSmith is a Prompt to GDS Agentic Flow
☆50Oct 19, 2026Updated this week
Alternatives and similar repositories for coresmith
Users that are interested in coresmith are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 10 months ago
- TinyWhisper: An Open-Source Fully-Integrated Multi-Mode Short-Wave Transmitter for Amateur Radio Applications in 130-nm CMOS☆24Oct 14, 2026Updated last week
- OpenLayout: an open-source custom IC design environment (KLayout, xschem, ngspice, FasterCap). ASAP7 today, support for more PDKs coming.☆19Oct 13, 2026Updated last week
- Open Agentic Design Automation - The open agent interface for EDA: Agent–EDA Contract☆28Aug 12, 2026Updated 2 months ago
- Replace Tcl scripting with Python☆18Aug 25, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A GPU built from scratch which can render graphics and train ML models☆15Jul 4, 2026Updated 3 months ago
- ☆12Oct 10, 2024Updated 2 years ago
- ☆23Sep 28, 2026Updated 3 weeks ago
- ☆14Jan 21, 2025Updated last year
- ElemRV - End-to-end Open-Source RISC-V Microcontroller☆150Oct 1, 2026Updated 3 weeks ago
- The SoC for the introduction to chip design course spring 2026☆21May 22, 2026Updated 5 months ago
- A fast, open-source DRC (Design Rule Check) engine for GDSII layouts.☆61Oct 16, 2026Updated last week
- AI-native IC design plugin with MCP-EDA — from natural-language intent to verified silicon.☆28Updated this week
- SystemVerilog file list pruner☆19Sep 14, 2026Updated last month
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- mojito☆13May 1, 2018Updated 8 years ago
- RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32☆60Nov 16, 2023Updated 2 years ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- Tiny Tapeout Explorer is an interactive web-based visualization tool for exploring integrated circuit designs from the Tiny Tapeout commu…☆24Jul 30, 2026Updated 2 months ago
- IIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively s…☆1,145Updated this week
- Online viewer of Xschem schematic files☆36Dec 14, 2025Updated 10 months ago
- Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.☆40Jul 30, 2026Updated 2 months ago
- Hardware Agent☆36Oct 16, 2026Updated last week
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- SiliconCompiler Design Gallery☆80Oct 12, 2026Updated last week
- A library of open PDK packages☆138Oct 13, 2026Updated last week
- ☆15Jul 7, 2026Updated 3 months ago
- RTL-to-Vector-to-GDS☆90Apr 2, 2026Updated 6 months ago
- XLSynth: Accelerated HW Synthesis☆18Updated this week
- ☆13Nov 18, 2024Updated last year
- An Open-Source Full-Custom Silicon Compiler for High-Performance FPGA Fabrics☆21Aug 25, 2026Updated last month
- AI-native Chiplet design flow based on open-source EDA toolchain☆49Aug 4, 2026Updated 2 months ago
- Blender GDSII Importer with PDK Support☆140Oct 16, 2026Updated last week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ARCH hardware description language and compiler☆78Updated this week
- Integrated Circuit Layout☆63Feb 25, 2025Updated last year
- Small SERV-based SoC primarily for OpenMPW tapeout☆53Dec 18, 2025Updated 10 months ago
- Python-to-schematic generator for Cadence Virtuoso. Define circuits in Python, auto-generate CDL netlists and schematics.☆43Aug 25, 2026Updated last month
- Fixed point math library for SystemVerilog☆45Nov 14, 2024Updated last year
- An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled t…☆27Jun 14, 2026Updated 4 months ago
- RTL implementation of a performance/area optimized bfloat16 adder and multiplication.☆38Mar 28, 2026Updated 6 months ago