This repository explores writing cocotb-style tests in modern C++, using coroutines and strong typing, with the goal of maintaining a Python-like test style while potentially improving simulation performance.
☆29Feb 16, 2026Updated 7 months ago
Alternatives and similar repositories for cocotb-cpp
Users that are interested in cocotb-cpp are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- cocotb extension for nMigen☆17Feb 26, 2022Updated 4 years ago
- 10 Gigabit Ethernet MAC Core UVM Verification☆19Oct 5, 2023Updated 2 years ago
- Apheleia Verification Library. A Python based HDL verification library sitting on top of cocotb☆60Updated this week
- Calling a python function from SV, then have this python function call SV tasks. Useful for coding register sequences in python☆12Sep 23, 2022Updated 3 years ago
- ESnet general-purpose FPGA design library.☆14Sep 3, 2026Updated 2 weeks ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆40Aug 31, 2026Updated 2 weeks ago
- ☆15May 24, 2025Updated last year
- Analog Circuit Simulator☆25Sep 6, 2024Updated 2 years ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆21Aug 23, 2026Updated 3 weeks ago
- HDL-first mixed-signal co-simulation: embed ngspice circuits in Verilog through VPI☆65Updated this week
- FPGA systolic array AI engine☆36Jan 2, 2026Updated 8 months ago
- Coverview☆35Sep 10, 2026Updated last week
- Build a SystemVerilog Environment for an ALU, using OOP testbench components as; stimulus generator, driver, monitor, scoreboard. ALU was…☆10Mar 4, 2023Updated 3 years ago
- Catalyst N1 — Open source neuromorphic processor (Loihi 1 parity). 128 cores, 131K neurons, 14-opcode learning ISA, FPGA-validated on AWS…☆45Jun 2, 2026Updated 3 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆70Aug 18, 2021Updated 5 years ago
- Cocotb AHB Extension - AHB VIP☆25Dec 12, 2025Updated 9 months ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆44Mar 5, 2026Updated 6 months ago
- micro version of cocotb, to run on microcontrollers or desktop to get hardware in the loop☆26Feb 25, 2025Updated last year
- A data acquisition framework in Python and Verilog.☆48Updated this week
- C++ HDL (Hardware Description Language)☆50Updated this week
- ☆10May 27, 2026Updated 3 months ago
- Making cocotb testbenches that bit easier☆42Feb 28, 2026Updated 6 months ago
- Digital Design Equivalence Checking☆109Updated this week
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- The HW-CBMC and EBMC Model Checkers for Verilog☆115Updated this week
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆26Jul 9, 2025Updated last year
- Netlist API (and more) for EDA flow development☆162Updated this week
- A collection of cryptographic algorthms implemented in SystemVerilog☆20Jun 7, 2018Updated 8 years ago
- Open-source RTL logic simulator with GPU acceleration (Metal, CUDA, HIP/AMD)☆85Aug 10, 2026Updated last month
- This repository provides an automated shell script to set up a Verilator + UVM-based workflow using the [RTL2UVM](https://github.com/rpja…☆21Oct 21, 2025Updated 10 months ago
- Yet another RISC-V Simulator on the web, running on Webassembly! https://riscv.vercel.app/☆43May 2, 2024Updated 2 years ago
- Texas Instruments fork of the Connectivity Standards Alliance connectedhomeip repository☆16Updated this week
- CIRCT and Yosys interoperability, demonstrated with CHISEL☆18Feb 3, 2026Updated 7 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- RISC-V Verification Interface☆162Jun 11, 2026Updated 3 months ago
- Elements Software Development Kit☆13Jan 8, 2026Updated 8 months ago
- Read only mirror of SVN ChibiOS repository. Official forum http://forum.chibios.org Bugtracker http://sourceforge.net/projects/chibios☆18Sep 2, 2019Updated 7 years ago
- ☆43Dec 21, 2025Updated 8 months ago
- GF180 ASIC tapeout of a 2x2 MAC with DFT infrastructure☆74Aug 12, 2026Updated last month
- Open Logic FPGA Standard Library☆1,012Updated this week
- A flexible and scalable development platform for modern FPGA projects.☆47Aug 10, 2026Updated last month