antmicro / renode-verilator-integrationLinks
This repository contains sample code integrating Renode with Verilator
☆22Updated 3 months ago
Alternatives and similar repositories for renode-verilator-integration
Users that are interested in renode-verilator-integration are comparing it to the libraries listed below
Sorting:
- Framework Open EDA Gui☆68Updated 9 months ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated 2 months ago
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆34Updated this week
- Tool for generating multi-purpose makefiles for FPGA projects (clone of hdlmake from CERN)☆17Updated 4 years ago
- Raptor end-to-end FPGA Compiler and GUI☆84Updated 9 months ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆83Updated last week
- Demo SoC for SiliconCompiler.☆60Updated last week
- ☆32Updated last week
- ☆23Updated 4 months ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated 2 months ago
- An abstract language model of VHDL written in Python.☆56Updated 2 months ago
- Spen's Official OpenOCD Mirror☆50Updated 6 months ago
- VHDL PCIe Transceiver☆30Updated 5 years ago
- FreeRTOS for PULP☆13Updated 2 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Updated 11 months ago
- System on Chip toolkit for Amaranth HDL☆92Updated 11 months ago
- FPGA tool performance profiling☆102Updated last year
- FuseSoC standard core library☆147Updated 3 months ago
- Naive Educational RISC V processor☆88Updated 2 months ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆106Updated last week
- Open Source AES☆31Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated last week
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- ☆14Updated 2 months ago
- Extensible FPGA control platform☆62Updated 2 years ago
- This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).☆17Updated 6 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆61Updated 5 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 3 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 3 years ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆51Updated 2 years ago