antmicro / renode-verilator-integrationLinks
This repository contains sample code integrating Renode with Verilator
☆25Updated 6 months ago
Alternatives and similar repositories for renode-verilator-integration
Users that are interested in renode-verilator-integration are comparing it to the libraries listed below
Sorting:
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated 2 months ago
- Raptor end-to-end FPGA Compiler and GUI☆91Updated 11 months ago
- Small SERV-based SoC primarily for OpenMPW tapeout☆47Updated 6 months ago
- FreeRTOS for PULP☆16Updated 2 years ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated last month
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆46Updated this week
- Extensible FPGA control platform☆61Updated 2 years ago
- 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.☆86Updated this week
- Framework Open EDA Gui☆73Updated 11 months ago
- VHDL PCIe Transceiver☆31Updated 5 years ago
- Sphinx Extension which generates various types of diagrams from Verilog code.☆63Updated 2 years ago
- ☆32Updated this week
- OSVVM UART Verification Components. Uart Transmitter with error injection for parity, stop, and break errors. UART Receiver verificati…☆13Updated 2 months ago
- Open Source AES☆31Updated 2 months ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆31Updated 3 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- Small footprint and configurable JESD204B core☆49Updated last month
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆63Updated 8 months ago
- This repository contain source code for ngspice and ghdl integration☆33Updated 11 months ago
- Demo SoC for SiliconCompiler.☆62Updated 2 weeks ago
- Generic Logic Interfacing Project☆48Updated 5 years ago
- A pipelined RISC-V processor☆62Updated 2 years ago
- cryptography ip-cores in vhdl / verilog☆41Updated 4 years ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆31Updated last week
- ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆36Updated this week
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆52Updated 2 years ago
- FuseSoC standard core library☆149Updated 6 months ago
- Example of how to use UVM with Verilator☆28Updated last week
- Spen's Official OpenOCD Mirror☆50Updated 8 months ago