Alternatives and similar repositories for renode-verilator-integration:

Users that are interested in renode-verilator-integration are comparing it to the libraries listed below

• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last month
• b224hisl / rioschip
  ☆33Updated 2 years ago
• AlSaqr-platform / he-soc
  ☆31Updated this week
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆49Updated last month
• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆44Updated 2 years ago
• chipsalliance / python-fpga-interchange
  Python interface to FPGA interchange format
  ☆41Updated 2 years ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago
• aignacio / nox
  RISC-V Nox core
  ☆62Updated last month
• dbhi / vboard
  Virtual development board for HDL design
  ☆42Updated 2 years ago
• pulp-platform / hyperbus
  ☆23Updated 2 weeks ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆54Updated 4 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 11 months ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated last month
• pulp-platform / neureka
  2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters
  ☆24Updated this week
• pulp-platform / trdb
  RISC-V processor tracing tools and library
  ☆16Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• ben-marshall / verilog-doc
  A basic documentation generator for Verilog, similar to Doxygen.
  ☆11Updated 8 years ago
• ee-uet / UETRV-PCore
  Linux Capable 32-bit RISC-V based SoC in System Verilog
  ☆60Updated 5 months ago
• ecilasun / e32e
  Latest in the line of the E32 processors with better/generic cache placement
  ☆10Updated 2 years ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆47Updated 4 years ago
• RISCV-on-Microsemi-FPGA / CPUs
  CPUs
  ☆14Updated 4 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆27Updated 9 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆20Updated 3 years ago
• Open-Source-Hardware-Initiative / AES
  Open Source AES
  ☆31Updated last year
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆55Updated last year