Digital logic benchmark suite
☆95Oct 27, 2026Updated this week
Alternatives and similar repositories for logikbench
Users that are interested in logikbench are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆42Oct 16, 2026Updated 2 weeks ago
- RTLMeter benchmark suite☆34Updated this week
- Demo: how to create a custom EBRICK☆30Nov 20, 2024Updated last year
- A ROHD-based framework for connectivity and assembly of hardware designs.☆14Sep 9, 2026Updated last month
- OpenLayout: an open-source custom IC design environment (KLayout, xschem, ngspice, FasterCap). ASAP7 today, support for more PDKs coming.☆19Updated this week
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- RTL-to-GDS: syn -> sta -> pnr -> gds☆15Sep 1, 2026Updated 2 months ago
- Open-source SystemVerilog simulator in Rust. 4-state, event-driven, IEEE 1800-2023, runs real UVM.☆123Updated this week
- 🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation☆13Apr 30, 2026Updated 6 months ago
- 55nm CMOS Open Source PDK for Digital, Analog, and Mixed-Signal Circuit Design. It supports an open-source RTL2GDS workflow for education…☆328Updated this week
- Source-available SystemVerilog RTL for a custom FPGA Ethernet datapath with ARP, IPv4, UDP, and specialized TCP transport control.☆42Jul 30, 2026Updated 3 months ago
- Open-source EDA framework for RTL elaboration, netlist analysis, and transformation, with C++ and Python APIs☆166Updated this week
- Custom IC Design Platform☆124Updated this week
- The VE-HEP RTL and Firmware☆12Mar 19, 2024Updated 2 years ago
- ☆14Aug 17, 2026Updated 2 months ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆35Feb 2, 2026Updated 9 months ago
- HDL-first mixed-signal co-simulation: embed ngspice circuits in Verilog through VPI☆77Sep 22, 2026Updated last month
- SystemVerilog design elaborator into word-level netlist form☆253Updated this week
- VS Code extension for SystemVerilog design navigation, RTL tracing, schematic viewer, and waveform integration☆66Jul 25, 2026Updated 3 months ago
- openENOC is an open-source Ethernet-based NoC for scalable MPSoC systems, using Layer-2 frame switching to connect CPUs, accelerators and…☆28Oct 23, 2026Updated last week
- WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM depen…☆13Mar 30, 2026Updated 7 months ago
- ☆13Jul 3, 2020Updated 6 years ago
- Greyhound on IHP SG13G2 0.13 μm BiCMOS process☆112Aug 31, 2026Updated 2 months ago
- mWATTBAT: The open source Radar Chip☆12Sep 1, 2025Updated last year
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- A Verilog implementation of Multi-bit-throughput LFSR with an detailed document about LFSRs for HW design engineers☆10Jan 2, 2026Updated 10 months ago
- Spire is a Python embedded domain-specific language (DSL) for RTL generation. Its built-in optimizations reduce area and delay of circuit…☆51Oct 13, 2026Updated 2 weeks ago
- A tapeout-ready structure for hierarchical analog design (v0.1).☆26Jan 16, 2026Updated 9 months ago
- ☆39Oct 21, 2026Updated last week
- Self-contained RTL to GDS flow for simple chip designs☆76Jul 7, 2026Updated 3 months ago
- Collection of digital hardware modules & projects (benchmarks)☆113Feb 27, 2026Updated 8 months ago
- A fast, open-source DRC (Design Rule Check) engine for GDSII layouts.☆62Updated this week
- FPGA synthesis tool☆146Oct 13, 2026Updated 2 weeks ago
- RTLScout is a agentic RTL optimization framework☆67Oct 26, 2026Updated last week
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Translate Chisel hardware design code to Scala simulation code.☆15May 15, 2025Updated last year
- Mirror of tachyon-da cvc Verilog simulator☆58Mar 16, 2026Updated 7 months ago
- TAIDL: Tensor Accelerator ISA Definition Language☆25Oct 20, 2026Updated last week
- Using e-graphs for logic synthesis (ICCAD'25)☆38Aug 28, 2026Updated 2 months ago
- IHP SG13CMOS5L PDK☆19Sep 23, 2026Updated last month
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- An easy-to-use, silicon-proven (e)FPGA generator with an integrated CAD toolchain 🏗️☆315Updated this week