Custom IC Design Platform
☆46Mar 3, 2026Updated this week
Alternatives and similar repositories for ordec
Users that are interested in ordec are comparing it to the libraries listed below
Sorting:
- For mosbius.org website☆30Jul 31, 2025Updated 7 months ago
- A tapeout-ready structure for hierarchical analog design (v0.1).☆25Jan 16, 2026Updated last month
- Open-source PDK version manager☆40Nov 25, 2025Updated 3 months ago
- ☆14Dec 27, 2024Updated last year
- A tiny Python package to parse spice raw data files.☆53Dec 26, 2022Updated 3 years ago
- Yet Another XC7Z010 Board☆17Mar 22, 2022Updated 3 years ago
- ☆14Sep 4, 2025Updated 6 months ago
- ☆20Apr 19, 2024Updated last year
- SpiceBind – spice inside HDL simulator☆57Jun 30, 2025Updated 8 months ago
- Scalable Interface for RISC-V ISA Extensions☆23Mar 1, 2026Updated last week
- SystemVerilog RTL Linter for YoSys☆23Nov 22, 2024Updated last year
- RTL data structure☆64Feb 20, 2026Updated 2 weeks ago
- How to correctly write a flicker-noise model for RF simulation.☆25Sep 19, 2025Updated 5 months ago
- A simple MOSFET model with only 5-DC-parameters for circuit simulation☆50Sep 8, 2025Updated 6 months ago
- ☆120Feb 17, 2026Updated 2 weeks ago
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆177Aug 8, 2025Updated 7 months ago
- A schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy an…☆444Feb 28, 2026Updated last week
- 32-bit RISC-V Emulator☆27Feb 23, 2019Updated 7 years ago
- CVA6 softcore contest☆22Updated this week
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆72Updated this week
- HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…☆25Mar 5, 2025Updated last year
- Advanced integrated circuits 2023☆32Feb 25, 2024Updated 2 years ago
- Parasitic Extraction for KLayout☆39Updated this week
- Characterizer☆31Nov 19, 2025Updated 3 months ago
- Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)☆36Jul 24, 2025Updated 7 months ago
- Ancillary Material for the book "Systematic Design of Analog CMOS Circuits"☆182Oct 6, 2025Updated 5 months ago
- ☆21Nov 12, 2025Updated 3 months ago
- UVM components for DSP tasks (MODulation/DEModulation)☆14Mar 2, 2022Updated 4 years ago
- Projects published on controlpaths.com and hackster.io☆42Jul 18, 2022Updated 3 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- ☆340Jan 13, 2026Updated last month
- Hardware Description Library☆88Feb 17, 2026Updated 2 weeks ago
- IP Core Library - Published and maintained by the Open Source VHDL Group☆57Feb 18, 2026Updated 2 weeks ago
- A Python library for working with logic networks, synthesis, and optimization.☆74Updated this week
- This repository provides examples that demonstrates how to develop PSoC 4 MCU based analog designs. These examples help you to use periph…☆15Oct 27, 2018Updated 7 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆12Mar 20, 2023Updated 2 years ago
- A plugin to allow Jenkins Steps with Cadence vManager API☆10Jan 15, 2026Updated last month
- Amperka ROS robot.☆12Aug 22, 2022Updated 3 years ago
- Простейшая VGA-видеокарта на Atmega168-20.☆10Apr 4, 2020Updated 5 years ago