A collection of datapath circuit design and verification benchmarks
☆19Jul 9, 2026Updated last month
Alternatives and similar repositories for DatapathBench
Users that are interested in DatapathBench are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A Lean-embedded framework to verify Verilog modules☆15Updated this week
- ☆33Nov 2, 2025Updated 9 months ago
- TAIDL: Tensor Accelerator ISA Definition Language☆19Apr 28, 2026Updated 3 months ago
- Arithmetic multiplier benchmarks☆12Nov 13, 2017Updated 8 years ago
- RTLMeter benchmark suite☆31Jul 21, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- MLIR-in as a compiler stack for ucb-bar☆18Updated this week
- FYP on using e-graphs to solve smt bitvector problems☆16Jun 24, 2025Updated last year
- An advanced circuit-based sat solver☆39Feb 24, 2025Updated last year
- RISCV Core written in Calyx☆17Aug 16, 2024Updated last year
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆35Aug 25, 2024Updated last year
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- Differentiable Combinatorial Scheduling at Scale (ICML'24). Mingju Liu, Yingjie Li, Jiaqi Yin, Zhiru Zhang, Cunxi Yu.☆23Oct 31, 2024Updated last year
- Verilog AST☆21Dec 2, 2023Updated 2 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A tool for cross-checking Verilog compilers☆15Apr 16, 2025Updated last year
- (WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases☆21May 2, 2026Updated 3 months ago
- APS: An open-source toolchain towards agile processor specialization based on MLIR☆19Jan 17, 2026Updated 6 months ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- easter egg is a flexible, high-performance e-graph library with support of multiple additional assumptions at once☆13Mar 27, 2025Updated last year
- Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving☆30Jan 7, 2026Updated 7 months ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated 2 years ago
- ☆17Jul 23, 2026Updated 2 weeks ago
- Rust bindings for CIRCT☆17Apr 20, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆18Jul 12, 2024Updated 2 years ago
- A tool for formally verifying constant-time software against hardware 🕰️☆16Feb 1, 2025Updated last year
- ☆18Feb 25, 2026Updated 5 months ago
- Refreshing automation for inductive equational proofs using e-graphs☆28Jul 7, 2024Updated 2 years ago
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆30Jun 23, 2025Updated last year
- design and verification of asynchronous circuits☆51Updated this week
- generating hardware accelerators for pangenomic graph queries☆45Jul 1, 2026Updated last month
- Tools for manipulating CHC and related files☆15Apr 21, 2023Updated 3 years ago
- A unified programming framework for high and portable performance across FPGAs and GPUs☆11Mar 23, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Fast Symbolic Repair of Hardware Design Code☆39Jan 20, 2025Updated last year
- LLM-Assisted Hardware Formal Verification Tool☆113Jul 13, 2026Updated 3 weeks ago
- Agile Hardware Design Course☆15Nov 17, 2025Updated 8 months ago
- Easy SMT solver interaction☆36Feb 3, 2026Updated 6 months ago
- A framework for formally verifying hardware security modules to be free of hardware, software, and timing side-channel vulnerabilities 🔏☆42Nov 29, 2025Updated 8 months ago
- work in progress, playing around with btor2 in rust☆15Jul 24, 2026Updated 2 weeks ago
- Formalizing the Intel 4004 microprocessor☆25Jul 14, 2026Updated 3 weeks ago