Agile Hardware Design Course
☆15Nov 17, 2025Updated 8 months ago
Alternatives and similar repositories for agile-hw
Users that are interested in agile-hw are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆25Oct 24, 2022Updated 3 years ago
- ☆20May 12, 2026Updated 2 months ago
- RTL implementation of a performance/area optimized bfloat16 adder and multiplication.☆33Mar 28, 2026Updated 4 months ago
- Lab material for the three week course on builiding a RISC-V microprocessor☆20Jan 14, 2026Updated 6 months ago
- A collection of datapath circuit design and verification benchmarks☆19Jul 9, 2026Updated last month
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆28Dec 4, 2025Updated 8 months ago
- The SoC for the introduction to chip design course spring 2026☆19May 22, 2026Updated 2 months ago
- ☆22Updated this week
- 本项目是一个基于RISC-V指令集架构的向量处理器(Vector Processing Unit, VPU)设计，旨在实现RISC-V向量扩展(RVV)规范中定义的向量运算功能。涵盖了处理器设计、计算机体系结构和硬件描述语言编程等多个领域的知识。☆20May 8, 2025Updated last year
- LibreLane full-chip flow template for IHP SG13G2 OpenPDK☆19Apr 20, 2026Updated 3 months ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- RISC-V RV32E core designed for minimal area☆27Nov 17, 2024Updated last year
- Connecting bv_decide to SMTLIB.☆16Updated this week
- work in progress, playing around with btor2 in rust☆15Jul 24, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Debug waveforms with GDB☆33Nov 12, 2025Updated 8 months ago
- Reconfigurable Stream Network Architecture☆18May 8, 2025Updated last year
- SKY130A implementatoin of the Blake2s hash algorithm☆26Dec 3, 2025Updated 8 months ago
- Self-contained RTL to GDS flow for simple chip designs☆73Jul 7, 2026Updated last month
- Hashing application☆13Aug 12, 2020Updated 5 years ago
- Notes on Common Lisp Libraries☆17Oct 16, 2024Updated last year
- Radix-4 1024 point fft in verilog☆12Apr 29, 2020Updated 6 years ago
- A RISC-V assembler library for Scala/Chisel HDL projects☆16Jul 14, 2026Updated 3 weeks ago
- ☆33Nov 2, 2025Updated 9 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Images from Unsplash straight to your desktop☆10Nov 27, 2015Updated 10 years ago
- A design for TinyTapeout☆19Sep 23, 2022Updated 3 years ago
- ☆15Sep 27, 2022Updated 3 years ago
- ☆13Apr 15, 2025Updated last year
- A tool for cross-checking Verilog compilers☆15Apr 16, 2025Updated last year
- Rust bindings for CIRCT☆17Apr 20, 2024Updated 2 years ago
- SimCommand is a library for writing high-performance RTL testbenches with simulation threads in Scala using chiseltest.☆15Aug 30, 2023Updated 2 years ago
- ☆31Sep 3, 2025Updated 11 months ago
- CoreSmith is a Prompt to GDS Agentic Flow☆35Updated this week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A fast, practical SystemVerilog LSP for RTL coding.☆37Updated this week
- Automated Analysis Framework for Simulink/Stateflow☆14Jul 25, 2023Updated 3 years ago
- ☆22Jun 14, 2026Updated last month
- ☆20Mar 3, 2026Updated 5 months ago
- Provides dot visualizations of chisel/firrtl circuits☆123Apr 14, 2023Updated 3 years ago
- verilog实现systolic array及配套IO☆15Dec 2, 2024Updated last year
- rv8 benchmark suite☆25Jul 30, 2020Updated 6 years ago