OPAE porting to Xilinx FPGA devices.
☆40Aug 5, 2020Updated 6 years ago
Alternatives and similar repositories for opae-xilinx
Users that are interested in opae-xilinx are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆53Jan 19, 2021Updated 5 years ago
- Virtio implementation in SystemVerilog☆49Jan 23, 2018Updated 8 years ago
- ☆35Jan 21, 2021Updated 5 years ago
- A platform for emulating Virtio devices with FPGAs☆29Mar 31, 2021Updated 5 years ago
- ☆21Jan 31, 2026Updated 6 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Virtio front-end and back-end bridge, implemented with FPGA.☆30Sep 16, 2020Updated 5 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Hardware Snappy decompressor☆12Sep 11, 2024Updated last year
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- A new kind of hardware decompressor for Snappy decompression. Much faster than the existing software one.☆24Jun 27, 2023Updated 3 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Aug 28, 2019Updated 6 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Jan 28, 2025Updated last year
- Extracting the dense depth map from plenoptic camera (Lytro)☆19Mar 19, 2018Updated 8 years ago
- Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)☆25Oct 30, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆77Aug 29, 2024Updated last year
- P4 compatible HLS modules☆11Apr 23, 2018Updated 8 years ago
- Latest in the line of the E32 processors with better/generic cache placement☆10Feb 25, 2023Updated 3 years ago
- FPU Generator☆20Updated this week
- Verilog-Based-NoC-Simulator☆12May 4, 2016Updated 10 years ago
- Extensible FPGA control platform☆63Apr 28, 2023Updated 3 years ago
- AMD OpenNIC Shell includes the HDL source files☆150Jan 2, 2025Updated last year
- An FPGA-based NetTLP adapter☆29Mar 10, 2020Updated 6 years ago
- A configurable general purpose graphics processing unit for☆12May 18, 2019Updated 7 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆15Jun 1, 2017Updated 9 years ago
- The RTL source for AnyCore RISC-V☆33Mar 18, 2022Updated 4 years ago
- PyMTL3 wrapper of the Berkeley Hardfloat IP☆10Aug 9, 2023Updated 3 years ago
- ☆20May 8, 2012Updated 14 years ago
- Centaur, a framework for hybrid CPU-FPGA databases☆28May 2, 2017Updated 9 years ago
- 🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes…☆46Mar 27, 2026Updated 4 months ago
- Open Programmable Acceleration Engine☆270Jul 10, 2026Updated last month
- General Purpose Graphics Processing Unit (GPGPU) IP Core☆11Jul 4, 2014Updated 12 years ago
- VHDL ieee_proposed library, imported as is. See also https://github.com/FPHDL/fphdl☆12Aug 26, 2016Updated 9 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Open-source FPGA research and prototyping framework.☆212Aug 8, 2024Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆74Aug 4, 2026Updated 2 weeks ago
- Kaggle Competition, Instance Segmentation☆86Apr 18, 2019Updated 7 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 10 years ago
- RISC-V soft-core PEs for TaPaSCo☆24Jul 24, 2026Updated 3 weeks ago
- A configuration controller solution allowing a Zynq device to configure downstream FPGAs☆14Oct 5, 2015Updated 10 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago