Alternatives and similar repositories for LowPower

Users that are interested in LowPower are comparing it to the libraries listed below

• avashist003 / FIFO_SystemVerilog_Assertion
  Synchronous FIFO design & verification using systemVerilog Assertions
  ☆17Updated 4 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆25Updated last year
• Anjali-287 / Synchronous-FIFO-UVM-TB
  UVM Testbench for synchronus fifo
  ☆19Updated 5 years ago
• isuckatdrifting / Gaia
  Generate UVM testbench framework template files with Python 3
  ☆27Updated 6 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆32Updated 5 years ago
• muneebullashariff / uart_vip
  Verification IP for UART protocol
  ☆22Updated 5 years ago
• loghall / axi_cache
  verification of simple axi-based cache
  ☆18Updated 6 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆35Updated 5 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆35Updated last week
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆47Updated last year
• chad-q / andes-vector-riscv-dv
  Andes Vector Extension support added to riscv-dv
  ☆17Updated 5 years ago
• taichi-ishitani / tvip-common
  ☆14Updated last year
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆25Updated 7 years ago
• Youssefmdany / 10-Gigabit-Ethernet-MAC-Core-UVM-Verification-
  10 Gigabit Ethernet MAC Core UVM Verification
  ☆16Updated 2 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆25Updated 6 years ago
• kei-seu / I2C
  UVM verification platform for DW_apb_i2c IP core(Master Mode)
  ☆11Updated 2 years ago
• forever-gk / AHB-SystemVerilog
  ☆17Updated 10 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆32Updated last year
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆15Updated 6 years ago
• pulp-platform / axi_spi_master
  ☆22Updated 6 years ago
• Mochenx / sv_csv_parser
  A CSV file parser, written in SystemVerilog
  ☆26Updated 9 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆18Updated 5 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆16Updated 5 years ago
• imokanj / clk_rst_agent
  UVM Clock and Reset Agent
  ☆14Updated 8 years ago
• ezchi / uvm-systemc
  My local copy of UVM-SystemC
  ☆14Updated last year
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆31Updated 11 months ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆36Updated 8 months ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆20Updated 5 years ago