Starting my 100 days verilog RTL, and basic system verilog coding challenge from , 21 may 2024
☆25Mar 20, 2025Updated last year
Alternatives and similar repositories for 100_DAYS_VERILOG_SV
Users that are interested in 100_DAYS_VERILOG_SV are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.☆11Apr 9, 2023Updated 3 years ago
- Verilog PCI express components☆26Jun 26, 2023Updated 2 years ago
- This repository is a summary of the RISC-V based MYTH workshop organised by VSD and Redwood EDA, made by Ahtesham Ahmed of grade 8.☆22May 12, 2025Updated last year
- ☆14Sep 27, 2022Updated 3 years ago
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆16Oct 18, 2014Updated 11 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- SRAM☆24Sep 6, 2020Updated 5 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆20Sep 8, 2020Updated 5 years ago
- Asynchronous fifo in verilog☆38Mar 20, 2016Updated 10 years ago
- Hierarchical Asynchronous Circuit Kompiler Toolkit☆24Dec 17, 2025Updated 6 months ago
- ECE 3300 HDL Code☆63Jan 21, 2023Updated 3 years ago
- Python API to Unified Coverage Interoperability Standard (UCIS) Data☆34Mar 7, 2026Updated 3 months ago
- ☆56Jun 19, 2021Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆62Mar 21, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆81Oct 10, 2022Updated 3 years ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆366Jan 12, 2018Updated 8 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆123Dec 29, 2024Updated last year
- ☆119Dec 24, 2023Updated 2 years ago
- SystemVerilog Tutorial☆226Mar 7, 2026Updated 3 months ago
- This repo provide an index of VLSI content creators and their materials☆171Aug 21, 2024Updated last year
- 100 Days of RTL☆418Aug 15, 2024Updated last year
- Open-source RTL logic simulator with CUDA acceleration☆279Sep 30, 2025Updated 8 months ago
- training labs and examples☆462Aug 1, 2022Updated 3 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …☆225Jun 5, 2026Updated 2 weeks ago
- Kactus2 is a graphical EDA tool based on the IP-XACT standard.☆255Jun 11, 2026Updated last week
- Python-based hardware modeling framework☆246Oct 27, 2019Updated 6 years ago
- A roadmap for those who want to build a career as an FPGA / ASIC Engineer☆623May 31, 2026Updated 2 weeks ago
- DRAMSys a SystemC TLM-2.0 based DRAM simulator.☆374May 29, 2026Updated 2 weeks ago
- BookSim 2.0☆430Jun 24, 2024Updated last year
- A open source reimplementation of Google's Tensor Processing Unit (TPU).☆758Dec 6, 2017Updated 8 years ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆797Jun 15, 2024Updated 2 years ago
- An open-source microcontroller system based on RISC-V☆1,040Feb 6, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A Python toolbox for building complex digital hardware☆1,327Jan 5, 2026Updated 5 months ago
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,599Updated this week
- cocotb: Python-based chip (RTL) verification☆2,407Updated this week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,969Updated this week
- Digital timing diagram rendering engine☆3,429Updated this week
- Verilator open-source SystemVerilog simulator and lint system☆3,693Updated this week
- Build your hardware, easily!☆3,953Updated this week