Alternatives and similar repositories for 100_DAYS_VERILOG_SV:

Users that are interested in 100_DAYS_VERILOG_SV are comparing it to the libraries listed below

• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆22Updated last year
• Khalique13 / dvsd_pe_sky130
  This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…
  ☆13Updated 3 years ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated last year
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆29Updated 5 years ago
• shubhi704 / APB-Protocol
  ☆41Updated 3 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆67Updated last year
• yathAg / openroad_vsd_7nmContest
  ☆14Updated last year
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆56Updated 11 months ago
• abdelazeem201 / ASIC-implementation-of-AES
  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…
  ☆20Updated 3 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆85Updated last year
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆122Updated 2 years ago
• OrsuVenkataKrishnaiah1235 / RTL-Coding
  "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
  ☆15Updated last year
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆100Updated 2 months ago
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆9Updated 6 months ago
• amiq-consulting / svaunit
  SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)
  ☆75Updated 4 years ago
• Artityagi123456789 / 15DaysofUVM
  ☆14Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆56Updated 2 years ago
• raysalemi / Python4RTLVerification
  ☆149Updated 2 years ago
• arunkpv / vsd-hdp
  ☆15Updated 8 months ago
• ShonTaware / OpenSource_Physical_Design
  This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
  ☆38Updated 3 years ago
• Ummidichandrika / 100-Days-of-RTL
  ☆107Updated last year
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆42Updated 4 years ago
• yuravg / uvm_tb_cross_bar
  SystemVerilog UVM testbench example
  ☆30Updated 10 months ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆125Updated 6 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆71Updated 3 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• kerimturak / tcore-rv32imc
  ☆12Updated 3 weeks ago
• karribharathi / 100-Days-of-RTL
  ☆16Updated last year