kunalg123 / vsdflowLinks
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW ta…
☆159Updated 2 years ago
Alternatives and similar repositories for vsdflow
Users that are interested in vsdflow are comparing it to the libraries listed below
Sorting:
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- Introductory course into static timing analysis (STA).☆94Updated last month
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆62Updated 2 years ago
- ☆159Updated 2 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆102Updated 4 years ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆330Updated last week
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆254Updated 3 months ago
- A complete open-source design-for-testing (DFT) Solution☆153Updated last week
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆177Updated 5 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆113Updated last year
- Standard Cell Library based Memory Compiler using FF/Latch cells☆147Updated 11 months ago
- ☆166Updated 2 months ago
- Fully Open Source FASOC generators built on top of open-source EDA tools☆280Updated 2 weeks ago
- ☆41Updated 3 years ago
- ☆78Updated 2 years ago
- ☆146Updated 3 years ago
- Static Timing Analysis Full Course☆56Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆69Updated 4 years ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆180Updated 3 weeks ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆83Updated 9 months ago
- Control and Status Register map generator for HDL projects☆116Updated last week
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆21Updated 2 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆121Updated this week
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- ☆15Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆62Updated last year
- Home of the open-source EDA course.☆41Updated 2 months ago