VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW ta…
☆169Apr 1, 2026Updated 4 months ago
Alternatives and similar repositories for vsdflow
Users that are interested in vsdflow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project has files needed to design and characterise flipflop☆21Jun 3, 2019Updated 7 years ago
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆26Aug 12, 2022Updated 4 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆85Nov 26, 2020Updated 5 years ago
- This repository is created for conducting RISC-V 5-day workshops☆23Jul 29, 2020Updated 6 years ago
- Physical Design Flow from RTL to GDS using Opensource tools.☆135Nov 23, 2020Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…☆126Jul 31, 2021Updated 5 years ago
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Oct 18, 2021Updated 4 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆235Oct 26, 2024Updated last year
- OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology sc…☆1,921Mar 25, 2026Updated 5 months ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆14Nov 23, 2020Updated 5 years ago
- ☆21Aug 4, 2022Updated 4 years ago
- ☆42Feb 28, 2022Updated 4 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆49Dec 6, 2020Updated 5 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆53Feb 22, 2022Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Open Analog Design Environment☆26May 19, 2023Updated 3 years ago
- A High-performance Timing Analysis Tool for VLSI Systems☆714Dec 26, 2025Updated 8 months ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆34Nov 25, 2024Updated last year
- This repository in a walk through the entire process of PLL IC designing from the tools to the final tapeout.☆21Feb 16, 2022Updated 4 years ago
- Python script for generating Xilinx .coe files for RAM initializing☆20Jan 3, 2019Updated 7 years ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆443Updated this week
- ☆19Sep 16, 2022Updated 3 years ago
- 64-bit MISC Architecture CPU☆13Dec 13, 2016Updated 9 years ago
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆19Sep 15, 2020Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆56Jan 4, 2022Updated 4 years ago
- An abstraction library for interfacing EDA tools☆790Aug 12, 2026Updated 2 weeks ago
- Magic VLSI Layout Tool☆695Updated this week
- opensource EDA tool flor VLSI design☆38Sep 17, 2023Updated 2 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆19Jul 21, 2020Updated 6 years ago
- Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users ca…☆21Aug 23, 2026Updated last week
- A complete open-source design-for-testing (DFT) Solution☆203Aug 30, 2025Updated last year
- Completed LDO Design for Skywaters 130nm☆21Feb 16, 2023Updated 3 years ago
- ☆95Jan 15, 2025Updated last year
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.☆3,678Jul 21, 2026Updated last month
- OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/☆3,039Updated this week
- crap-o-scope scope implementation for icestick☆20Jun 1, 2018Updated 8 years ago
- DATC Robust Design Flow.☆36Jan 21, 2020Updated 6 years ago
- Learn, share and collaborate on ASIC design using open tools and technologies☆12Dec 27, 2020Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆50Nov 18, 2024Updated last year
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆253Updated this week