kunalg123 / vsdflowLinks
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW ta…
☆163Updated 2 years ago
Alternatives and similar repositories for vsdflow
Users that are interested in vsdflow are comparing it to the libraries listed below
Sorting:
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆78Updated 5 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- ☆174Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆46Updated 5 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆71Updated 3 years ago
- Introductory course into static timing analysis (STA).☆99Updated 6 months ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆162Updated 2 months ago
- ☆42Updated 3 years ago
- A complete open-source design-for-testing (DFT) Solution☆176Updated 4 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆45Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆185Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆117Updated 5 years ago
- ☆187Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 4 years ago
- Functional Coverage and Constrained Randomization Extensions for Cocotb☆118Updated 3 months ago
- An implementation of the CORDIC algorithm in Verilog.☆107Updated 7 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆81Updated 4 years ago
- Static Timing Analysis Full Course☆63Updated 3 years ago
- Qflow full end-to-end digital synthesis flow for ASIC designs☆223Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆99Updated last year
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆206Updated last year
- Basic RISC-V Test SoC☆166Updated 6 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆189Updated this week
- This script builds openlane and all its dependencies on an Ubuntu (only) System.☆23Updated 3 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆104Updated last year
- AXI4 and AXI4-Lite interface definitions☆102Updated 5 years ago
- PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open p…☆383Updated 2 weeks ago
- Logic synthesis and ABC based optimization☆51Updated last month
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi …☆54Updated 4 years ago
- Verilog digital signal processing components☆168Updated 3 years ago