amradel2020 / vlsi_linkedin_indexLinks
This repo provide an index of VLSI content creators and their materials
☆160Updated last year
Alternatives and similar repositories for vlsi_linkedin_index
Users that are interested in vlsi_linkedin_index are comparing it to the libraries listed below
Sorting:
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆278Updated 6 months ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆120Updated 3 years ago
- ☆117Updated last year
- 100 Days of RTL☆402Updated last year
- ☆15Updated 2 years ago
- SystemVerilog Tutorial☆182Updated last week
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆101Updated 2 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆122Updated 2 years ago
- Verilog HDL files☆160Updated last year
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆170Updated 4 months ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆15Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆95Updated last year
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆20Updated 4 years ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆25Updated 10 months ago
- opensource EDA tool flor VLSI design☆35Updated 2 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆81Updated 3 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆31Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆165Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆29Updated last year
- ☆170Updated 3 years ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆30Updated 4 months ago
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆195Updated 3 weeks ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆64Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆34Updated 3 months ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆20Updated 2 years ago
- ☆22Updated 2 years ago