akilm / Physical-DesignLinks
Physical Design Flow from RTL to GDS using Opensource tools.
☆106Updated 4 years ago
Alternatives and similar repositories for Physical-Design
Users that are interested in Physical-Design are comparing it to the libraries listed below
Sorting:
- Introductory course into static timing analysis (STA).☆94Updated last week
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆72Updated 4 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆180Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆70Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- Logic synthesis and ABC based optimization☆49Updated last week
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆64Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆94Updated last year
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆161Updated 2 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆102Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆66Updated last year
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆186Updated 2 months ago
- ☆27Updated last week
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- Standard Cell Library based Memory Compiler using FF/Latch cells☆151Updated last week
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆90Updated 10 months ago
- A complete open-source design-for-testing (DFT) Solution☆161Updated last month
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆120Updated this week
- A Standalone Structural Verilog Parser☆93Updated 3 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆168Updated 7 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆46Updated 4 years ago
- ☆41Updated last year
- Basic RISC-V Test SoC☆137Updated 6 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated 4 months ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆132Updated last year