akilm / Physical-DesignLinks
Physical Design Flow from RTL to GDS using Opensource tools.
☆105Updated 4 years ago
Alternatives and similar repositories for Physical-Design
Users that are interested in Physical-Design are comparing it to the libraries listed below
Sorting:
- Introductory course into static timing analysis (STA).☆96Updated last month
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆73Updated 4 years ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆161Updated 2 years ago
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆181Updated 5 years ago
- Verilog/SystemVerilog Guide☆69Updated last year
- Logic synthesis and ABC based optimization☆49Updated 3 weeks ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆257Updated last week
- IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)☆186Updated 2 months ago
- A Standalone Structural Verilog Parser☆96Updated 3 years ago
- A complete open-source design-for-testing (DFT) Solution☆162Updated 2 months ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- Curriculum for a university course to teach chip design using open source EDA tools☆102Updated last year
- ☆157Updated 3 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- Static Timing Analysis Full Course☆57Updated 2 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆69Updated last year
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆104Updated 2 months ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆127Updated last week
- OpenROAD users should look at this repository first for instructions on getting started☆101Updated 4 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 2 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆46Updated 4 years ago
- ☆161Updated 2 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆73Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- ☆178Updated 4 months ago
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆92Updated 11 months ago