Alternatives and similar repositories for 100Daysof_RTL

Users that are interested in 100Daysof_RTL are comparing it to the libraries listed below

• nhandyal / Verilog-Spectrum-Analyzer
  FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.
  ☆14Updated 13 years ago
• eescottie / opensrc_analog
  Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design
  ☆11Updated last month
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆41Updated last year
• Manish4403 / RISC_V_with_ICACHE
  ☆13Updated 9 months ago
• abdelazeem201 / SoC-Implementation-of-OpenMSP430-Microcontroller
  The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…
  ☆15Updated 3 years ago
• abdelazeem201 / ASIC-Implementation-UART
  This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…
  ☆14Updated 3 years ago
• Deverne-labs / TinyML-Zybo
  This repository is a collection of designs invloving FPGAs and AI technologies.
  ☆14Updated 2 years ago
• kumarrishav14 / AMBA_APB
  To design test bench of the APB protocol
  ☆17Updated 4 years ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆44Updated 3 years ago
• sarthak268 / Embedded_Logic_and_Design
  This repository contains all labs done as a part of the Embedded Logic and Design course.
  ☆23Updated 7 years ago
• wnew / hdl_library
  A library of verilog and vhdl modules
  ☆15Updated 6 years ago
• taneroksuz / cpu-medium
  6-stage in-order dual-issue superscalar risc-v cpu with floating point unit
  ☆14Updated last month
• mihir8181 / VLSI-Design-Digital-System
  This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…
  ☆32Updated 6 years ago
• vsdip / vsdsram_sky130
  ☆42Updated 3 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆31Updated 4 years ago
• kunalg123 / sky130RTLDesignAndSynthesisWorkshop
  ☆11Updated 3 years ago
• IUST-Computer-Organization / LUMOS
  Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor
  ☆48Updated 7 months ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆27Updated 2 weeks ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• VardhanSuroshi / VLSI-ASIC-Design-Flow
  This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…
  ☆19Updated last year
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆20Updated 2 years ago
• SubZer0811 / VLSI
  All the projects and assignments done as part of VLSI course.
  ☆20Updated 4 years ago
• Youssefmdany / 10-Gigabit-Ethernet-MAC-Core-UVM-Verification-
  10 Gigabit Ethernet MAC Core UVM Verification
  ☆14Updated last year
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆65Updated 2 years ago
• iammituraj / pqr5asm
  PQR5ASM is a RISC-V Assembler compliant with RV32I
  ☆19Updated 4 months ago
• RClabiisc / I2SRV64-SS-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆24Updated last year
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆44Updated 3 years ago
• Suntrakanesh / System-Verilog-bootcamp
  System Verilog BootCamp
  ☆25Updated 3 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆57Updated 2 months ago