maazm007 / 100Daysof_RTLLinks
The Repository contains the code of various Digital Circuits
☆11Updated 2 years ago
Alternatives and similar repositories for 100Daysof_RTL
Users that are interested in 100Daysof_RTL are comparing it to the libraries listed below
Sorting:
- ☆44Updated last year
- ☆13Updated 11 months ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆14Updated 3 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated last month
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆14Updated 13 years ago
- This repository contains all labs done as a part of the Embedded Logic and Design course.☆26Updated 7 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆16Updated 3 years ago
- Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design☆11Updated 4 months ago
- To design test bench of the APB protocol☆18Updated 4 years ago
- This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other detai…☆33Updated 6 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- ☆19Updated 3 years ago
- This repository is a collection of designs invloving FPGAs and AI technologies.☆14Updated 2 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- ☆43Updated 3 years ago
- Light Utilization with Multicycle Operational Stages (LUMOS) RISC-V Processor☆48Updated 10 months ago
- Design & Implementation of Multi Clock Domain System using Verilog HDL☆14Updated 2 years ago
- ☆17Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆33Updated 4 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆30Updated 3 years ago
- Verilog RTL Design☆45Updated 4 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆52Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆92Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆82Updated 4 years ago
- RTL Design and Verification☆17Updated 4 years ago
- Open source ISS and logic RISC-V 32 bit project☆61Updated 3 weeks ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆67Updated 3 years ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Updated 7 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated 2 years ago