kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
☆28Updated 11 months ago
Alternatives and similar repositories for DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING:
Users that are interested in DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING are comparing it to the libraries listed below
- ☆12Updated last month
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆38Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆66Updated 3 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 7 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆55Updated 2 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆15Updated 3 years ago
- ☆40Updated 3 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆15Updated 8 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆14Updated 2 years ago
- Complete tutorial code.☆17Updated 10 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆22Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆15Updated 9 months ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆16Updated 11 months ago
- ☆10Updated 2 years ago
- ☆13Updated 3 months ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆65Updated 4 years ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- ☆17Updated 2 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated 2 weeks ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆17Updated 4 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated last year
- DMA Hardware Description with Verilog☆13Updated 5 years ago