☆48Apr 7, 2024Updated 2 years ago
Alternatives and similar repositories for DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
Users that are interested in DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Design of 4KB(1024*32) SRAM with operating voltage 1.8v and access time < 2.5ns☆16Dec 8, 2020Updated 5 years ago
- Catalyst N1 — Open source neuromorphic processor (Loihi 1 parity). 128 cores, 131K neurons, 14-opcode learning ISA, FPGA-validated on AWS…☆36Jun 2, 2026Updated last month
- RISC V core implementation using Verilog.☆30Mar 27, 2021Updated 5 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆34Nov 25, 2024Updated last year
- LLM-aided Hardware Design and Verification☆34May 11, 2026Updated last month
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Home of the open-source EDA course.☆54Jun 12, 2025Updated last year
- Documentation for the 2025 IEEE SSCS Chipathon Track on MOSbius☆18Sep 6, 2025Updated 10 months ago
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆32Jul 21, 2025Updated 11 months ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Apr 15, 2018Updated 8 years ago
- ☆11Sep 9, 2022Updated 3 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆49Dec 6, 2020Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆83Nov 26, 2020Updated 5 years ago
- Semiconductor Packaging Fundamentals☆33May 19, 2025Updated last year
- Design and UVM-TB of RISC -V Microprocessor☆34Jun 27, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆25Nov 11, 2025Updated 7 months ago
- Free to use tokenizers trained on the Darija language.☆15Mar 26, 2025Updated last year
- My notes for DDR3 SDRAM controller☆54Feb 23, 2023Updated 3 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- Tutorials for getting started with an f8 softcore on an FPGA board☆13Aug 17, 2025Updated 10 months ago
- Implementation of a RISC-V CPU in Verilog.☆17Jun 27, 2026Updated last week
- Desktop app for lithography learning available for Windows, macOS, and Linux☆13Sep 2, 2023Updated 2 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆59Updated this week
- Collect some IC specs for learning.☆24Jun 25, 2024Updated 2 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- This project was done as a part of Beginner VLSI/SoC Physical design using open-source EDA Tools workshop.☆13Nov 23, 2020Updated 5 years ago
- Reusable 4-bit CPU in Logisim with Verilog HDL, ISA docs, and a browser playground☆14Feb 24, 2026Updated 4 months ago
- ☆14Sep 27, 2022Updated 3 years ago
- ☆15Dec 2, 2021Updated 4 years ago
- This repository is a summary of the RISC-V based MYTH workshop organised by VSD and Redwood EDA, made by Ahtesham Ahmed of grade 8.☆21May 12, 2025Updated last year
- Convolutional Neural Network Implemented in Verilog for System on Chip☆28Apr 18, 2019Updated 7 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Formal Verification of RISC V IM Processor☆11Mar 27, 2022Updated 4 years ago
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- ☆13Jun 10, 2026Updated last month
- CVA6 softcore contest☆24Updated this week
- Building a simple oscilloscope using FPGA board and PCB.☆22Dec 30, 2020Updated 5 years ago
- Simulator that maintains coherent caches for 4, 8 and 16 core CMP. Implementation of MSI, MESI, MOSI, MOESI and MOESIF protocols for a b…☆11Jan 6, 2015Updated 11 years ago
- 『컴퓨터 시스템 딥 다이브』(한빛미디어, 2023) 예제 코드 저장소입니다.☆10Dec 28, 2023Updated 2 years ago
- The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso☆62Mar 21, 2024Updated 2 years ago
- A FIFO or Queue is an array of memory commonly used in hardware to transfer transfer data between two circuits with different clocks. The…☆16Nov 5, 2017Updated 8 years ago