kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNINGLinks
☆41Updated last year
Alternatives and similar repositories for DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
Users that are interested in DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING are comparing it to the libraries listed below
Sorting:
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆66Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆73Updated 4 years ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- ☆41Updated 3 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆73Updated 4 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆69Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 11 months ago
- Curriculum for a university course to teach chip design using open source EDA tools☆102Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆44Updated 3 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆13Updated 8 months ago
- ☆12Updated 4 months ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆46Updated 4 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated 2 years ago
- Design Verification Engineer interview preparation guide.☆24Updated 2 weeks ago
- This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…☆18Updated last year
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆35Updated 2 years ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆73Updated 2 years ago
- Introductory course into static timing analysis (STA).☆96Updated last month
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆20Updated 2 months ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆25Updated last year
- Physical Design Flow from RTL to GDS using Opensource tools.☆105Updated 4 years ago
- ☆17Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆62Updated 8 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated last year
- General Purpose AXI Direct Memory Access☆55Updated last year
- Xilinx AXI VIP example of use☆41Updated 4 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆68Updated 7 months ago