RISC-V RV32I CPU core
☆35Mar 3, 2023Updated 3 years ago
Alternatives and similar repositories for RISC-V-RV32I
Users that are interested in RISC-V-RV32I are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆13Apr 18, 2024Updated 2 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆62Jul 5, 2024Updated last year
- ☆14Sep 27, 2022Updated 3 years ago
- Verilog implementation of the ASCON lightweight authenticated encryption and hashing algorithm☆10Nov 27, 2024Updated last year
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- FPGA examples on Google Colab☆29Feb 24, 2026Updated 2 months ago
- ☆18Apr 24, 2023Updated 3 years ago
- ☆15May 8, 2018Updated 7 years ago
- A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.☆30Nov 18, 2025Updated 5 months ago
- ☆42Jan 10, 2024Updated 2 years ago
- Project in Course named DESIGN AND IMPLEMENTATION OF COMMUNICATION PROTOCOLS in FCU☆15Oct 18, 2014Updated 11 years ago
- ☆10Apr 20, 2026Updated last week
- Design and Simulation of 1K * 32 bit SRAM memory design.☆17Dec 15, 2021Updated 4 years ago
- This repository provides examples that demonstrates how to develop PSoC 4 MCU based analog designs. These examples help you to use periph…☆15Oct 27, 2018Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆364Jan 12, 2018Updated 8 years ago
- RISC-V microcontroller IP core for embedded, FPGA and ASIC applications☆195Apr 18, 2026Updated 2 weeks ago
- ☆24Nov 4, 2023Updated 2 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- A submodule of Chipyard https://github.com/ucb-bar/chipyard☆20Oct 22, 2025Updated 6 months ago
- Hardware Design of Ascon☆43Apr 13, 2026Updated 2 weeks ago
- ☆23Jun 23, 2024Updated last year
- Ring Oscillator Physically Unclonable Funtion☆25Sep 9, 2021Updated 4 years ago
- 基于物联网技术以及人脸识别技术,系统底层采用ESP32开发板为核心,在ESP32开发板上接入了红外对管传感器、蜂鸣器、电磁锁等元器件,当有人暴力开锁触发红外报警信息时,便会通过蜂鸣器报警。应用层PC端使用摄像头实现人脸识别,实现用户登录以及收银台解锁,通过TCP协议与云主机…☆16Jul 4, 2021Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆13Jan 4, 2021Updated 5 years ago
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆28Jul 11, 2024Updated last year
- ☆19Jul 21, 2020Updated 5 years ago
- The SparkFun RED-V RedBoard is a low-cost, development board featuring the Freedom E310 SoC which brings with it the RISC-V instruction s…☆19Dec 12, 2019Updated 6 years ago
- 🔮 A 16-bit MIPS Processor Implementation in Verilog HDL☆12Aug 30, 2020Updated 5 years ago
- Programmable System on Chip for control of atomic physics experiments☆11Sep 13, 2022Updated 3 years ago
- STLink library with WebUSB☆12Jan 2, 2022Updated 4 years ago
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- a simple command line tool for downloading YouTube video using node.js☆34Oct 11, 2013Updated 12 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Compliant controller for the Kinova Gen3 arm☆32Oct 21, 2025Updated 6 months ago
- MuJoCo motion planning library.☆22Updated this week
- RQml is your modern, QML-based robotics visualization and control toolbox for ROS 2!☆31Apr 20, 2026Updated last week
- An advanced, next-gen debate evidence collector.☆12Apr 17, 2022Updated 4 years ago
- A ROS2 interface to PyBullet☆14Updated this week
- Zenoh ROS-like Middleware☆33Apr 18, 2026Updated 2 weeks ago
- Applied YOLO model trained on COCO dataset to detect obstacles and Lane-Net model trained on tusimple.ai dataset for end-to-end lane dete…☆12Jun 16, 2020Updated 5 years ago