akash10295 / VLSI-Design-FrontEnd-plus-BackEnd
☆12Updated 6 years ago
Alternatives and similar repositories for VLSI-Design-FrontEnd-plus-BackEnd:
Users that are interested in VLSI-Design-FrontEnd-plus-BackEnd are comparing it to the libraries listed below
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆75Updated last year
- ☆43Updated 3 years ago
- Architectural design of data router in verilog☆29Updated 5 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆10Updated 8 months ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆35Updated 5 years ago
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆68Updated 4 years ago
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆13Updated 3 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year
- ☆10Updated 2 years ago
- A complete UVM TB for verification of single port 64KB RAM☆15Updated 4 years ago
- ☆16Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆41Updated 3 years ago
- UVM and System Verilog Manuals☆41Updated 6 years ago
- ☆40Updated last year
- ☆17Updated last year
- ☆16Updated last year
- opensource EDA tool flor VLSI design☆32Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆44Updated 4 years ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆19Updated last year
- ☆16Updated 9 months ago
- ☆22Updated last year
- IEEE Executive project for the year 2021-2022☆9Updated 2 years ago
- A collection of commonly asked RTL design interview questions☆27Updated 7 years ago
- ☆14Updated last year
- ☆15Updated 2 years ago
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆23Updated 10 months ago