xuanz20 / Network-on-Chip-VerilogLinks
A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.
☆14Updated 2 years ago
Alternatives and similar repositories for Network-on-Chip-Verilog
Users that are interested in Network-on-Chip-Verilog are comparing it to the libraries listed below
Sorting:
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Updated 2 months ago
 - RTL code of some arbitration algorithm☆14Updated 6 years ago
 - Router 1 x 3 verilog implementation☆14Updated 4 years ago
 - tpu-systolic-array-weight-stationary☆24Updated 4 years ago
 - Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆13Updated 2 years ago
 - Implementation of the PCIe physical layer☆56Updated 3 months ago
 - This project is to design yolo AI accelerator in verilog HDL.☆28Updated last year
 - ☆64Updated 3 years ago
 - Design and UVM-TB of RISC -V Microprocessor☆28Updated last year
 - OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆17Updated 7 months ago
 - Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆15Updated last year
 - Bitonic sorter (Batcher's sorting network) written in Verilog.☆35Updated last year
 - LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
 - ☆14Updated 2 years ago
 - L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆14Updated 3 years ago
 - ☆26Updated 4 years ago
 - 包括同步FIFO(输入输出位宽相同),异步FIFO(输入输出位宽相同),异步FIFO(能实现输出数据位宽是输入数据位宽的1/2或2倍)☆22Updated 2 years ago
 - CNN accelerator using NoC architecture☆16Updated 6 years ago
 - CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
 - The memory model was leveraged from micron.☆24Updated 7 years ago
 - 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例,并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆26Updated 2 years ago
 - 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
 - MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆12Updated 2 years ago
 - NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
 - verification of simple axi-based cache☆18Updated 6 years ago
 - - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Updated 6 years ago
 - ☆37Updated 6 years ago
 - Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
 - DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
 - work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago