xuanz20 / Network-on-Chip-VerilogLinks
A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.
☆16Updated 2 years ago
Alternatives and similar repositories for Network-on-Chip-Verilog
Users that are interested in Network-on-Chip-Verilog are comparing it to the libraries listed below
Sorting:
- Tensor Processing Unit implementation in Verilog☆11Updated 9 months ago
- Router 1 x 3 verilog implementation☆14Updated 4 years ago
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆14Updated 3 months ago
- Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-ma…☆14Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- RTL code of some arbitration algorithm☆15Updated 6 years ago
- tpu-systolic-array-weight-stationary☆25Updated 4 years ago
- ☆39Updated 6 years ago
- ☆31Updated 5 years ago
- MIPS Processor, BNN Accelerator, AXI4 interface, Cache Controller and LRU replacement☆13Updated 3 years ago
- Implementation of the PCIe physical layer☆59Updated 5 months ago
- Template for project1 TPU☆21Updated 4 years ago
- ☆79Updated 11 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆35Updated last year
- This project is to design yolo AI accelerator in verilog HDL.☆28Updated last year
- ☆28Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 2 years ago
- Design and UVM-TB of RISC -V Microprocessor☆32Updated last year
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- ☆26Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆55Updated 4 years ago
- YSYX RISC-V Project NJU Study Group☆16Updated 11 months ago
- Network-on-Chip simulator (Booksim) with hooks for co-simulating RTL designs in Verilog.☆24Updated 10 years ago
- ☆66Updated 3 years ago
- Verilog and matlab implementation of tanh using Cordic algorithm☆11Updated 5 years ago
- ☆14Updated 2 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆38Updated 8 years ago
- CNN accelerator using NoC architecture☆17Updated 7 years ago
- TinyVers Heterogeneous SoC consists of a reconfigurable FlexML accelerator, a RISC-V processor, an eMRAM and a power management system.☆23Updated 2 years ago