A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.
☆21May 30, 2023Updated 3 years ago
Alternatives and similar repositories for Network-on-Chip-Verilog
Users that are interested in Network-on-Chip-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL design and implementation of a 4x4 Network-on-Chip (NoC) with a mesh topology. This project includes SystemVerilog modules for buffer…☆32Jul 12, 2024Updated 2 years ago
- ☆15Oct 27, 2024Updated last year
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆19Oct 6, 2024Updated last year
- LSTM neural network (verilog)☆16Dec 5, 2018Updated 7 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Jan 6, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A parametric RTL code generator of an efficient integer MxM Systolic Array implementation for Xilinx FPGAs, with error detection capabili…☆15Aug 28, 2025Updated last year
- ☆26Aug 10, 2023Updated 3 years ago
- AES☆16Oct 4, 2022Updated 3 years ago
- 16QAM modulation and demodulation by Verilog☆20Jan 4, 2021Updated 5 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆16Jun 20, 2022Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆77Dec 30, 2019Updated 6 years ago
- This is a simple VLIW based processor written in Verilog. A Python script has also been included to simulate static instruction schedulin…☆19May 14, 2021Updated 5 years ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 7 years ago
- ☆19Aug 22, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- IC Verification & SV Demo☆60Sep 29, 2021Updated 4 years ago
- A verilog implementation for Network-on-Chip☆88Feb 3, 2018Updated 8 years ago
- Tensor Processing Unit implementation in Verilog☆16Aug 12, 2026Updated last month
- Starting my 100 days verilog RTL, and basic system verilog coding challenge from , 21 may 2024☆27Mar 20, 2025Updated last year
- Ratatoskr NoC Simulator☆30Apr 13, 2021Updated 5 years ago
- Verilog library for implementing neural networks.☆27Aug 19, 2014Updated 12 years ago
- ☆29Oct 20, 2019Updated 6 years ago
- A code to solve 8 Puzzle game using A star algorithm.☆10Aug 19, 2019Updated 7 years ago
- UART in Verilog and VHDL☆18Aug 21, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 5 years ago
- Revise Spark written in Rust (Native Spark or Vega) to a secure one☆11Apr 7, 2023Updated 3 years ago
- Cycle Accurate Network-on-Chip Simulator☆38Jul 11, 2026Updated 2 months ago
- ☆14Jul 1, 2018Updated 8 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni