ZipCPU / openartyLinks
An Open Source configuration of the Arty platform
☆132Updated last year
Alternatives and similar repositories for openarty
Users that are interested in openarty are comparing it to the libraries listed below
Sorting:
- A utility for Composing FPGA designs from Peripherals☆185Updated 11 months ago
- FuseSoC standard core library☆149Updated 6 months ago
- Collection of open-source peripherals in Verilog☆183Updated 3 years ago
- A wishbone controlled scope for FPGA's☆84Updated last year
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆70Updated 3 years ago
- VHDL library 4 FPGAs☆181Updated this week
- This repository contains small example designs that can be used with the open source icestorm flow.☆153Updated 4 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆92Updated 7 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- A Video display simulator☆174Updated 6 months ago
- A FPGA core for a simple SDRAM controller.☆123Updated 4 years ago
- Wishbone interconnect utilities☆43Updated 9 months ago
- Verilog implementation of a RISC-V core☆131Updated 7 years ago
- Verilog wishbone components☆123Updated last year
- SoftCPU/SoC engine-V☆55Updated 8 months ago
- Yet Another RISC-V Implementation☆99Updated last year
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 6 years ago
- Project X-Ray Database: XC7 Series☆73Updated 3 years ago
- SoC based on VexRiscv and ICE40 UP5K☆157Updated 8 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆92Updated 3 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆136Updated 3 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Extensible FPGA control platform☆61Updated 2 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- Small footprint and configurable embedded FPGA logic analyzer☆197Updated last month
- CMod-S6 SoC☆43Updated 7 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆42Updated 9 years ago