ZipCPU / openarty
An Open Source configuration of the Arty platform
☆124Updated last year
Alternatives and similar repositories for openarty:
Users that are interested in openarty are comparing it to the libraries listed below
- A utility for Composing FPGA designs from Peripherals☆170Updated last month
- A wishbone controlled scope for FPGA's☆74Updated last year
- FuseSoC standard core library☆125Updated this week
- Yet Another RISC-V Implementation☆86Updated 4 months ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆116Updated 8 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.☆134Updated 2 years ago
- Extensible FPGA control platform☆56Updated last year
- Collection of open-source peripherals in Verilog☆173Updated 2 years ago
- Project X-Ray Database: XC7 Series☆65Updated 3 years ago
- ☆127Updated last month
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Verilog wishbone components☆113Updated last year
- This repository contains small example designs that can be used with the open source icestorm flow.☆143Updated 3 years ago
- Verilog digital signal processing components☆125Updated 2 years ago
- Verilog implementation of a RISC-V core☆108Updated 6 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆84Updated 6 years ago
- Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs☆161Updated 10 months ago
- SoftCPU/SoC engine-V☆54Updated last year
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆79Updated 5 years ago
- SoC based on VexRiscv and ICE40 UP5K☆152Updated 9 months ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆67Updated 2 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆94Updated 2 years ago
- USB Serial on the TinyFPGA BX☆135Updated 3 years ago
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- A Video display simulator☆160Updated 6 months ago
- Wishbone interconnect utilities☆38Updated 8 months ago