An Open Source configuration of the Arty platform
☆131Jan 17, 2024Updated 2 years ago
Alternatives and similar repositories for openarty
Users that are interested in openarty are comparing it to the libraries listed below
Sorting:
- ☆48May 18, 2016Updated 9 years ago
- A ZipCPU based demonstration of the MAX1000 FPGA board☆23May 11, 2021Updated 4 years ago
- A simple, basic, formally verified UART controller☆326Jan 29, 2024Updated 2 years ago
- A utility for Composing FPGA designs from Peripherals☆186Dec 23, 2024Updated last year
- A ZipCPU demonstration port for the icoboard☆19Oct 21, 2021Updated 4 years ago
- CMod-S6 SoC☆45Jan 6, 2018Updated 8 years ago
- Bus bridges and other odds and ends☆639Apr 14, 2025Updated 10 months ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆26Apr 6, 2019Updated 6 years ago
- A small, light weight, RISC CPU soft core☆1,509Dec 8, 2025Updated 2 months ago
- ☆487Jul 15, 2025Updated 7 months ago
- Xilinx Bitstream Format Library. Easily read .bit files from C programs.☆14Nov 16, 2015Updated 10 years ago
- A wishbone controlled PWM (audio) controller☆18Jan 16, 2024Updated 2 years ago
- Parallel Array of Simple Cores. Multicore processor.☆100May 16, 2019Updated 6 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆97Oct 31, 2022Updated 3 years ago
- SoftCPU/SoC engine-V☆56Mar 19, 2025Updated 11 months ago
- A 32-bit MIPS processor which aims for conformance to the MIPS32 Release 1 ISA.☆19Jul 29, 2015Updated 10 years ago
- ☆16Dec 5, 2025Updated 2 months ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆417Feb 20, 2026Updated last week
- This repository contains small example designs that can be used with the open source icestorm flow.☆156Sep 25, 2021Updated 4 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- A wishbone controlled scope for FPGA's☆88Jan 12, 2024Updated 2 years ago
- FPGA display controller with support for VGA, DVI, and HDMI.☆247Jan 28, 2026Updated last month
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆22Nov 25, 2015Updated 10 years ago
- Verilog library for ASIC and FPGA designers☆1,392May 8, 2024Updated last year
- System on Chip with RISCV-32 / RISCV-64 / RISCV-128☆22Updated this week
- A Real Time Clock core for FPGA's☆28Jan 17, 2024Updated 2 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- My repositories for Icestudio.☆13Jul 14, 2025Updated 7 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆92Aug 10, 2018Updated 7 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆44May 12, 2016Updated 9 years ago
- A Verilog implementation of DisplayPort protocol for FPGAs☆266Mar 15, 2019Updated 6 years ago
- Tiny CPU is a small 32-bit CPU done mostly as a hobby for educational purposes.☆35Jan 17, 2012Updated 14 years ago
- Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module☆21Feb 8, 2018Updated 8 years ago
- A Video display simulator☆177May 16, 2025Updated 9 months ago
- SDIO Device Verilog Core☆24Jul 25, 2018Updated 7 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,026Feb 11, 2026Updated 2 weeks ago
- Cortex-M3 development tree☆15Jan 4, 2015Updated 11 years ago
- The Numato Opsis board is the first fully open source HDMI2USB board.☆13Sep 8, 2015Updated 10 years ago
- Bonfire SoC running on FireAnt FPGA Board☆12Feb 11, 2024Updated 2 years ago