Alternatives and similar repositories for VLSI-Project-AXI-to-APB-Bridge

Users that are interested in VLSI-Project-AXI-to-APB-Bridge are comparing it to the libraries listed below

• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆24Updated 2 weeks ago
• kerimturak / tcore-rv32imc
  ☆13Updated 5 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆65Updated 2 years ago
• vritrv / ROUTER-1X3-RTL-DESIGN
  Architectural design of data router in verilog
  ☆31Updated 5 years ago
• Devipriya1921 / VSDBabySoC_ICC2
  ☆13Updated 3 years ago
• yathAg / openroad_vsd_7nmContest
  ☆15Updated 2 years ago
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆157Updated last year
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆12Updated last year
• Ghonimo / Pre_Silicon-AHB-to_APB-Verification
  Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀
  ☆32Updated last year
• shubhi704 / APB-Protocol
  ☆47Updated 4 years ago
• Vidhi24-hub / 100daysofrtl
  ☆16Updated last year
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆82Updated last year
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆63Updated last year
• ShashankSirohiya / 100DaysOfRtl
  I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.
  ☆24Updated 2 years ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆93Updated 2 years ago
• semiDESIgner / 50daysRTLcode
  ☆17Updated 2 years ago
• raysalemi / Python4RTLVerification
  ☆165Updated 3 years ago
• chinthacharan / DV-Interview-Prep-Guide
  Design Verification Engineer interview preparation guide.
  ☆35Updated last month
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆60Updated 2 years ago
• basemhesham / Design-and-ASIC-Implementation-of-UART
  This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been impl…
  ☆21Updated last year
• Artityagi123456789 / -100dasofSystemVerilog
  System Verilog using Functional Verification
  ☆12Updated last year
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆50Updated 5 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆76Updated 4 years ago
• Ummidichandrika / 100-Days-of-RTL
  ☆115Updated last year
• KOTHAVANI / 100-Days-of-RTL-code
  ☆42Updated 2 years ago
• daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules
  Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
  ☆14Updated last year
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated 2 years ago
• Khalique13 / dvsd_pe_sky130
  This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…
  ☆14Updated 3 years ago
• VardhanSuroshi / VLSI-ASIC-Design-Flow
  This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specificatio…
  ☆21Updated last year
• fayizferosh / yosys-tcl-ui-report
  5 Day TCL begginer to advanced training workshop by VSD
  ☆18Updated last year