aseddin / ece_3300Links
ECE 3300 HDL Code
☆58Updated 2 years ago
Alternatives and similar repositories for ece_3300
Users that are interested in ece_3300 are comparing it to the libraries listed below
Sorting:
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆412Updated 3 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆272Updated 5 months ago
- This repo provide an index of VLSI content creators and their materials☆160Updated last year
- 100 Days of RTL☆401Updated last year
- ☆117Updated last year
- Verilog HDL files☆155Updated last year
- ☆86Updated 2 months ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆119Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆160Updated last year
- SystemVerilog Tutorial☆178Updated this week
- This repository is dedicated to exploring the practical aspects of analog electronic circuits and Analog VLSI design. It contains a colle…☆25Updated last year
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆142Updated 3 weeks ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆14Updated 2 years ago
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆25Updated 9 months ago
- Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…☆113Updated 3 weeks ago
- lowRISC Style Guides☆461Updated 4 months ago
- opensource EDA tool flor VLSI design☆35Updated 2 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆152Updated 4 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Updated 3 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆80Updated 3 years ago
- ☆36Updated last year
- ☆166Updated 3 years ago
- Verilog implementation of multi-stage 32-bit RISC-V processor☆137Updated 5 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆100Updated 2 years ago
- ☆22Updated 2 years ago
- ☆13Updated last year
- ☆16Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆67Updated 3 years ago
- ☆352Updated 2 years ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆185Updated last week