ZipCPU / qspiflashLinks
A set of Wishbone Controlled SPI Flash Controllers
☆92Updated 3 years ago
Alternatives and similar repositories for qspiflash
Users that are interested in qspiflash are comparing it to the libraries listed below
Sorting:
- Open-source high performance AXI4-based HyperRAM memory controller☆80Updated 3 years ago
- Small (Q)SPI flash memory programmer in Verilog☆65Updated 3 years ago
- Verilog SPI master and slave☆62Updated 9 years ago
- UART -> AXI Bridge☆67Updated 4 years ago
- WISHBONE SD Card Controller IP Core☆128Updated 3 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆82Updated last year
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆76Updated 3 years ago
- I2C controller core☆47Updated 2 years ago
- Verilog wishbone components☆124Updated last year
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆158Updated 9 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆41Updated 2 months ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Verilog digital signal processing components☆159Updated 3 years ago
- Wishbone interconnect utilities☆43Updated 9 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- Verilog UART☆186Updated 12 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆70Updated 5 years ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆40Updated 4 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆30Updated 2 years ago
- USB 2.0 Device IP Core☆72Updated 8 years ago
- AHB3-Lite Interconnect☆104Updated last year
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆102Updated this week
- UART 16550 core☆37Updated 11 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆123Updated 5 years ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- ☆137Updated 11 months ago