A set of Wishbone Controlled SPI Flash Controllers
☆97Oct 31, 2022Updated 3 years ago
Alternatives and similar repositories for qspiflash
Users that are interested in qspiflash are comparing it to the libraries listed below
Sorting:
- Small (Q)SPI flash memory programmer in Verilog☆68Nov 5, 2022Updated 3 years ago
- Wishbone controlled I2C controllers☆57Nov 12, 2024Updated last year
- Wishbone interconnect utilities☆44Feb 23, 2026Updated last week
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆21Nov 21, 2017Updated 8 years ago
- A wishbone controlled PWM (audio) controller☆18Jan 16, 2024Updated 2 years ago
- SD-Card controller, using either SPI, SDIO, or eMMC interfaces☆356Oct 18, 2025Updated 4 months ago
- SPI-Flash XIP Interface (Verilog)☆48Oct 24, 2021Updated 4 years ago
- ☆14Jun 30, 2019Updated 6 years ago
- Various projects of SPI loader module for xilinx fpga☆33Jul 20, 2020Updated 5 years ago
- WISHBONE Interconnect☆11Oct 1, 2017Updated 8 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 7 years ago
- SPI core☆12Jul 17, 2014Updated 11 years ago
- ☆12Jul 20, 2022Updated 3 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- VexRiscV system with GDB-Server in Hardware☆21Jul 5, 2023Updated 2 years ago
- SDRAM controller with multiple wishbone slave ports☆30Oct 26, 2018Updated 7 years ago
- Verilog wishbone components☆124Jan 5, 2024Updated 2 years ago
- A simple, basic, formally verified UART controller☆326Jan 29, 2024Updated 2 years ago
- Fractional interpolation using a Farrow structure☆10Oct 11, 2023Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Jul 17, 2014Updated 11 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- USB -> AXI Debug Bridge☆42Jun 5, 2021Updated 4 years ago
- SSD test project using Zynq Ultrascale+ bare metal NVMe.☆22Oct 8, 2021Updated 4 years ago
- WISHBONE SD Card Controller IP Core☆130Sep 17, 2022Updated 3 years ago
- A series of CORDIC related projects☆121Nov 12, 2024Updated last year
- FPGA纯逻辑实现modbus通信☆22Sep 5, 2022Updated 3 years ago
- QSPI for SoC☆23Nov 8, 2019Updated 6 years ago
- A wishbone controlled scope for FPGA's☆88Jan 12, 2024Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆42Jan 18, 2024Updated 2 years ago
- Imaging application using MIPI and DisplayPort to process image☆25Feb 13, 2020Updated 6 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆24Nov 7, 2018Updated 7 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Apr 15, 2018Updated 7 years ago
- Bus bridges and other odds and ends☆639Apr 14, 2025Updated 10 months ago
- Minimal DVI / HDMI Framebuffer☆83Aug 9, 2020Updated 5 years ago
- Arcade: Pacman for MiSTer☆23Jan 12, 2026Updated last month
- I2C controller core from Opencores.org☆27Oct 5, 2011Updated 14 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- ☆10Oct 18, 2024Updated last year