freecores / wb_dmaLinks
WISHBONE DMA/Bridge IP Core
☆18Updated 11 years ago
Alternatives and similar repositories for wb_dma
Users that are interested in wb_dma are comparing it to the libraries listed below
Sorting:
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Updated 5 years ago
- Generic AXI master stub☆19Updated 11 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆45Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- ☆21Updated 5 years ago
- ☆21Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench☆14Updated 5 years ago
- APB Logic☆19Updated 2 weeks ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- NoC based MPSoC☆11Updated 11 years ago
- Various low power labs using sky130☆13Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- Implementation of the PCIe physical layer☆48Updated 2 months ago
- ☆16Updated 6 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- Pipelined FFT/IFFT 64 points processor☆11Updated 11 years ago
- - Designed a Nand Flash Controller, Flash Memory and Buffer (Design Target : Samsung K9F1G08R0A NAND Flash). - Implemented operations : …☆21Updated 7 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 5 years ago
- Repository gathering basic modules for CDC purpose☆54Updated 5 years ago
- Reed Solomon Decoder (204,188)☆12Updated 11 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 4 years ago
- To design test bench of the APB protocol☆17Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆53Updated 4 years ago
- UART -> AXI Bridge☆62Updated 4 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 11 years ago