freecores / wb_dmaLinks
WISHBONE DMA/Bridge IP Core
☆18Updated 10 years ago
Alternatives and similar repositories for wb_dma
Users that are interested in wb_dma are comparing it to the libraries listed below
Sorting:
- PCI bridge☆18Updated 10 years ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- ☆16Updated 6 years ago
- Generic AXI master stub☆19Updated 10 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆20Updated 5 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- Pipelined FFT/IFFT 64 points processor☆12Updated 10 years ago
- ☆21Updated 5 years ago
- APB Logic☆18Updated 5 months ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆17Updated 5 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Collection of IPs based on AMBA (AHB, APB, AXI) protocols☆19Updated 8 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- ☆14Updated 5 years ago
- 100 MB/s Ethernet MAC Layer Switch☆15Updated 10 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago
- Implementation of the PCIe physical layer☆40Updated 3 weeks ago
- DSP WishBone Compatible Cores☆13Updated 10 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- AXI DMA Check: A utility to measure DMA speeds in simulation☆15Updated 4 months ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- A Verilog AMBA AHB Multilayer interconnect generator☆12Updated 7 years ago