ZipCPU / cordic
A series of CORDIC related projects
☆94Updated 2 months ago
Alternatives and similar repositories for cordic:
Users that are interested in cordic are comparing it to the libraries listed below
- Verilog digital signal processing components☆120Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆149Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆63Updated 2 years ago
- Mathematical Functions in Verilog☆86Updated 3 years ago
- A collection of demonstration digital filters☆142Updated last year
- An implementation of the CORDIC algorithm in Verilog.☆86Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- RTL Verilog library for various DSP modules☆84Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆141Updated last year
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆49Updated 2 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆61Updated 4 years ago
- SpinalHDL Hardware Math Library☆82Updated 6 months ago
- Fixed Point Math Library for Verilog☆124Updated 10 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- Small (Q)SPI flash memory programmer in Verilog☆57Updated 2 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- Extensible FPGA control platform☆55Updated last year
- A simple DDR3 memory controller☆53Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆100Updated last year
- configurable cordic core in verilog☆47Updated 10 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆61Updated 3 weeks ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆130Updated last month
- Verilog wishbone components☆113Updated last year
- Generic FIFO implementation with optional FWFT☆55Updated 4 years ago
- Verilog SPI master and slave☆48Updated 9 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆74Updated this week
- I2C controller core☆35Updated 2 years ago
- Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.☆52Updated this week