ZipCPU / cordicLinks
A series of CORDIC related projects
☆110Updated 9 months ago
Alternatives and similar repositories for cordic
Users that are interested in cordic are comparing it to the libraries listed below
Sorting:
- A collection of phase locked loop (PLL) related projects☆108Updated last year
- Verilog digital signal processing components☆150Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆87Updated 2 years ago
- Verilog wishbone components☆117Updated last year
- Extensible FPGA control platform☆62Updated 2 years ago
- A collection of demonstration digital filters☆155Updated last year
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆116Updated 4 years ago
- SpinalHDL Hardware Math Library☆90Updated last year
- ☆99Updated last year
- Open-source high performance AXI4-based HyperRAM memory controller☆76Updated 2 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆62Updated last year
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆94Updated last week
- A configurable C++ generator of pipelined Verilog FFT cores☆246Updated last year
- ☆135Updated 8 months ago
- Mathematical Functions in Verilog☆94Updated 4 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆85Updated 5 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆61Updated 3 years ago
- An implementation of the CORDIC algorithm in Verilog.☆98Updated 6 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆88Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- I2C Master Verilog module☆35Updated 2 months ago
- FuseSoC standard core library☆147Updated 3 months ago
- A simple implementation of a UART modem in Verilog.☆151Updated 3 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆60Updated 4 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆39Updated 5 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆154Updated 5 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year