A series of CORDIC related projects
☆125Nov 12, 2024Updated last year
Alternatives and similar repositories for cordic
Users that are interested in cordic are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A wishbone controlled PWM (audio) controller☆18Jan 16, 2024Updated 2 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Apr 15, 2024Updated 2 years ago
- A collection of demonstration digital filters☆175Jan 18, 2024Updated 2 years ago
- An implementation of the CORDIC algorithm in Verilog.☆110Nov 19, 2018Updated 7 years ago
- A configurable C++ generator of pipelined Verilog FFT cores☆258Apr 18, 2024Updated 2 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A set of Wishbone Controlled SPI Flash Controllers☆102Oct 31, 2022Updated 3 years ago
- Wishbone controlled I2C controllers☆57Nov 12, 2024Updated last year
- Turbo coder and decoder☆12Oct 11, 2023Updated 2 years ago
- FPGA tutorial☆22Oct 3, 2020Updated 5 years ago
- Wishbone SATA Controller☆26Oct 16, 2025Updated 7 months ago
- configurable cordic core in verilog☆54Jul 17, 2014Updated 11 years ago
- InnovateFPGA☆14Apr 30, 2018Updated 8 years ago
- ☆15Dec 2, 2021Updated 4 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆20Nov 13, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- A Motorola 68000 Computer☆24Jun 1, 2019Updated 7 years ago
- A small, light weight, RISC CPU soft core☆1,550Dec 8, 2025Updated 6 months ago
- A 4x4x4 Tic-Tac-Toe game suitable for porting to embedded hardware platforms☆11Sep 6, 2017Updated 8 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Dec 9, 2020Updated 5 years ago
- SDRAM controller with multiple wishbone slave ports☆30Oct 26, 2018Updated 7 years ago
- PCB layout for my cheap FPGA HDMI experimenting board☆10Aug 21, 2014Updated 11 years ago
- Digital Interpolation Techniques Applied to Digital Signal Processing☆69Jun 24, 2024Updated last year
- 10Gb Ethernet Switch☆265Oct 16, 2025Updated 7 months ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- The CORDIC algorithm implemented in Octave/MATLAB and Verilog☆32Mar 31, 2015Updated 11 years ago
- ☆13Dec 1, 2025Updated 6 months ago
- AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP☆17Nov 9, 2023Updated 2 years ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆32Nov 3, 2025Updated 7 months ago
- Implementation of CORDIC Algorithms Using Verilog☆26Apr 26, 2021Updated 5 years ago
- IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system☆21May 27, 2026Updated 2 weeks ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Dec 17, 2021Updated 4 years ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆18Jan 28, 2022Updated 4 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Reference FPGA designs for interfacing with the internal ARM Cortex M3 MCU of the GW1NSR-4C, modified for use with boards like the Tang N…☆12Aug 13, 2022Updated 3 years ago
- Asynchronous FIFO for transferring data between two asynchronous clock domains☆17Jun 3, 2016Updated 10 years ago
- An open-source Xilinx Kria SOM Carrier for high-speed camera design☆31Dec 25, 2023Updated 2 years ago
- Common SystemVerilog RTL modules for RgGen☆16Feb 5, 2026Updated 4 months ago
- Benchmarking execution time of AlexNet CNN on FPGA and GPU. Developed AlexNet in opencl.☆11Oct 9, 2019Updated 6 years ago
- The source code for the XTRX FPGA image☆17Nov 19, 2022Updated 3 years ago
- ☆15Sep 23, 2020Updated 5 years ago