olofk / wb_interconLinks
Wishbone interconnect utilities
☆41Updated 5 months ago
Alternatives and similar repositories for wb_intercon
Users that are interested in wb_intercon are comparing it to the libraries listed below
Sorting:
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆79Updated last year
- A set of Wishbone Controlled SPI Flash Controllers☆84Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆81Updated 4 years ago
- Verilog wishbone components☆116Updated last year
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- Minimal DVI / HDMI Framebuffer☆83Updated 4 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- TCP/IP controlled VPI JTAG Interface.☆67Updated 6 months ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- UART models for cocotb☆29Updated 2 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆52Updated 2 months ago
- ☆134Updated 7 months ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 5 months ago
- Portable HyperRAM controller☆56Updated 7 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.☆93Updated this week
- UART 16550 core☆37Updated 11 years ago
- ☆38Updated 4 years ago
- FuseSoC standard core library☆146Updated 2 months ago
- Wishbone controlled I2C controllers☆51Updated 8 months ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- Reusable Verilog 2005 components for FPGA designs☆45Updated 5 months ago
- Yet Another RISC-V Implementation☆96Updated 10 months ago
- Featherweight RISC-V implementation☆52Updated 3 years ago